I'm trying to define a circuit regression flow. From what I learned, there seems to be 2 options. I haven't looked too deep into either one. But I'd like to solicit some inputs first.
General Background* analog and mixed signal IP; roughly half circuit, half logic. * logic verification with behavioral models are expected to be OVM/UVM based* complexity of IP is high; many operating modes* circuit test plan include pure circuit sims and AMS sims.
Option #1 ADE XL based tests* organize circuit regression using ADE XL* create a ADEXL view for each main blocks; define tests/spec for those blocks* Use some script to run all the adexl views included in regression* many built-in measurements; good for debug; * a bit slow; not too friendly for reuse (for example, a block has a measurement; at high level, that same measurement may be needed as well; have to redefine the measurement.)* reuse ADEXL for another project or a similar block is not that straightforward
Option #2 OVM/UVM based env* converged flow with logic team; great for reuse* initial investment is big; not as easy to start as ADEXL* circuit team don't have verification expertise; no knowledge of "e".* not sure how hard it is to reproduce all the measurement available in calculator in "e"* seems to be more flexible; E.g. spec update or checking can be automated.* cdnlive 2010 has an example of this - LSI + Cadence
Again, I haven't looked too deep into either one yet. Just starting to use IC6.1, and UVM is relatively new too. I may be missing something... Please comment if you have experiences or opinions. Thanks.