If I have a transistor level schematic and my simulations show that my circuit is working correctly in virtuoso, how can I generate the verilog netlist and source code to be imported/included for Encounter to design the layout?
Thanks in advance!
You could use Tools->Simulation->NC Verilog (or Verilog XL) to invoke the Verilog netlister to produce a set of netlist files in the run directory. You'd probably need to concatenate them all together, or there's a solution on Cadence Online Support which explains how to set a variable which will produce a single netlist. I'm a bit busy, so I'll let you search for it yourself.
Alternatively, contact Cadence Customer Support and go through this in more detail as a service request.