I am using IC6.1.5-64b.500.12
When I call Instances from schematics to layout using "generate>selected from source", it places the instances multiple times. Also all the instances are placed at origin
Any idea why this is happening ? and how to solve this issue ?
I'd normally expect this if you have a parameter called m to act as a multiplier. If you don't want to have "m" treated as an m-factor, you can prevent that from the XL Options form.
In reply to Andrew Beckett:
Thanks andrew for quick reply. But unfortunately that did not help.
I have attached a snapshot for more clarifications.
thanks & reagards,
In reply to Roopak25:
Unfortunately I don't think I can help much seeing a picture at that level of detail - this would be best handled by you contacting customer support, and then somebody can take a look at your data (either by you sending it, or via remote web-sharing session).
Did you fix your multiple instances issue? I am facing the same issue and I don't know how to solve it.
In my particular case, I have a single inductor in the schematic and when I transition to layout XL, I get 5 instances of that inductor.
For those who want to take a look, please click on the picture to see the layout window as well.
In reply to gabriel rf:
This is probably because your inductor has a parameter called "s". Go to Options->Layout XL, and on the Parameters tab, in the section labelled "Schematic Parameter Names", change the cyclic field to "Series-connected factor". It's probably showing "s S" as the value. Change this to something that doesn't include "s" (e.g. "sdummy").
What it is probably doing is misinterpreting the s=5u as 5 series connected instances...
Thank you for your answer. I checked the settings you mention, even changed to sdummy, but that did not remove the extra instances. However, at some point they disappeared, but I can't tell for sure what I have done.
In the mean time, I took a different approach. I have manually instantiated the inductor, then I ran LVS to confirm the sync with the schematic. It worked and I've been able to run and plot simulations for the ideal schematic and the extracted circuit that includes the parasitics. The differences are visible.