can you please clarify what tools are you using? As far as RTL synthesis is concerned, most if not all synthesis tools in the market place do not perform any glitch mitigation so it is left to user to design circuity that is glitch tolerant. In fact, this is one of the reasons, why most synthesis tools are meant to be used for synchronous design and not asynchronous design. Glitches in such cases would lead to hazards, etc.
In reply to grasshopper: