I am are doing my UG Final year project using cadence gpdk 45nm technology,
It would be of great help if someone explain and help us find a solution for the following two error messages:
=> OXIDE.A.1:Minimum area for Active area >=0.035 um
=>METAL.A.1:Metal area must be >=0.02 um
These errors pertain to vias used- nwell and psub
Could someone also brief about the vias used for nmos and pmos in gpdk 45nm technology?
Thanks in advance!
Well, the metal area shouldn't be an issue because you'd want to route to them, presumably.
Similarly you'd usually ensure that the oxide (diffusion) is large enough - you can do this either by placing the via connected to an oxide region, or place a multiple via (set the rows or columns to 3 - this sets the area big enough that a standalone via would not cause an issue, but in practice you're going to want to connect it to something!).
I don't understand your last question.
In reply to Andrew Beckett:
Placing those two vias as stand alone via placements does not guarantee that they will be correct, they should be correct in a design context. As Andrew said, the metal meets the area rule when connected to a route. You placed the vias without interaction with any program (interactive router for example) so the enclosures to the cuts are not updated to the rules. You will have to modify the placements by increasing the enclosures or putting in more than one cut to meet the diffusion area rules.