can anyone describe what does "test fixture flag" mean exactly? And where can I find this option in ADEXL? I have searched the documentation with no success. I use IC_6.1.5HF132 64bit
Message from log file:
WARNING (VLOGNET-121): You are netlisting with the test fixture flag set to OFF.This could result in possible timescale directive violations. No timescale irective will be added by the netlister. Set the test fixture option to ONbefore netlisting if there are such violations.
Thank you very much for answer in advance.
My guess is that you're simulating using AMS? Or are you using spectreVerilog or ultrasimVerilog? Maybe you have one of these variables in a .simrc file or .cdsinit somewhere:
In Tools->NC Verilog, this corresponds to the "Generate Verilog Test Fixture Template" option on Setup->Netlist. In UltraSimVerilog (and spectreVerilog, I think - I only checked one of them), this is on Setup->Environment and then the "Verilog Netlist Option" button.
I don't know whether this impacts AMS simulation or not.
And it's only a warning...