I'm importing some verilog files into dfII library to
generate a schematic to run a transistor level simulation.The library
for standard cells are created first. When I use verilogin, it can
proceed without errors but there is a weird problem, it will place each
module twice, one with proper connections and one without any
For example, following is a simple verilog file, containing only one inverter.
module test (A, B, VDD, VSS);input A;output B;input VDD;input VSS;INHDV1 inv1 (.VSS ( VSS ), .VDD ( VDD ), .I ( A ), .ZN ( B ) );endmodule
module test (A, B, VDD, VSS);
INHDV1 inv1 (.VSS ( VSS ), .VDD ( VDD ), .I ( A ), .ZN ( B ) );
is a standard cell and it has ports VDD/VSS/I/ZN. But the imported
schematic has two inverters, where one connects to VDD/VSS/A/B
correctly, and the other has no connections at all.
I tried some options in verilogIn form and read the document. No clues. We are using IC5141usr6.
Could anybody give some suggestions?
I don't see this problem using IC5141 USR6. It works fine for me...
Do you have a particular version of the digital simulators in your path? From UNIX, what do you get if you type "ncvlog -version" (I was running without ncvlog in my path).
In reply to Andrew Beckett:
Very curious, the problem is gone after I switched to IC5141user5. Actually I'm using only ihdl from ic5141usr5 since this time I tried to use command line. After preparing the ihdl_files needed, I specify the path to call ihdl residing in 5141usr5, now everything is ok. Don't know why.
The version for ihdl in 5141usr5 is 5.1.0 06/20/2007, and for 5141usr6 it's 5.1.0 10/28/2008.
And ncvlog's version is 8.20-s024. ( But in ncvlog.log, it said 5.50-E115. )
Perhaps there are some compatible issues in my environment.
Thanks a lot,