We are using AMS Designer for high level verification on a chip with many analog blocks as well as two digital voltage domains.
We are invoking AMS Designer from ADE.
Now, when applying a digital (VerilogD) clock, we do see ripple on the analog power supply even thou we do not have any impedance on the power supply.(In reality we may have some impedance on the power supply but not in our simpler verilog-ams models.)
It seems like the modules(?) automatically inserted by the connect library cannot tell signal sources from power supply sources. (How could it? We have not told the netlister which is which.) Can we force this by any action?
It seems like a waste of CPU time to calculate the ripple when it should not be there.
It's quite possible that these are just numerical noise - it's hard to tell from your description. Particularly if you're using trapezoidal method, you may see some small oscillations between timepoints. It doesn't necessarily mean that more work is having to be done. Particularly since the digital events are probably causing analog timesteps, you may see numerical variations at these times, since there may not have been so many timesteps in the analog demain between the digital events.How big is this ripple?Andrew.
Also, the STANDARD AMS connect models DO have some output impeadance, (to cover the case where the connect module AND another voltage source (ie parallel connect module - or testbench source) both drive the net.. Too often the elaboration would fail if there was not a way for the connect modules to connect in parallel.. ) so there is a little (5 Ohm?) resistance - which you can change.. - don't think of it as the "simulator calculating ripple" .. its just multiplying the current times the resistance.. The time you spend worrying about it is going to be the biggest drain on your productivity. (In all probability)