I tried to simulate my pipeline ADC circuit which contains both Analog and Digital blocks. Earlier I tried with the Verilog-A coding instead of the verilog coding as I was unaware of the mixed simulators like SpectreVerilog and UltrasimVerilog. Now I included the digital verilog part also into the schmatic and simulated successfully with SPectreVerilog. But when I tried with Ultrasim the Verilog-A block failed to properly identify the Analog events. I activate my Verilog-A block only during cross +ve event but it generates glitches during other transitions of the clock also. similar problem occured with UltrasimVerilog with digital block producing glitches. Verilog block got activated during the negative clock transitios also whereas I programmed only for positive clock tranisitions. I checked whether there is any problem from the analog side but the analog side waveforms look normal. Is there any known solution to this problem??
This is unlikely to be a general problem, but specific to your data. I suggest you contact Cadence customer support where we can help you with this, looking at your specific data.Best Regards,Andrew.