I'm currently simulating a big mixed signal block, consisting of two big blocks. The instance block I0 is
pure digital logic, instance I1 is mainly analog but also includes some digital parts. I'm using Ultrasim
for verification but due to the analog parts I'm forced to use a quite strict accuracy setting to get the
results about right. However this setting is killing the digital part ...
I know that some other simulators offer the possibility to define accuracy levels for each instance in
a design, e.g. set I0 to Digital Fast and I1 to Analog. Is something like this possible with Ultrasim ?
This can be done in the hierarchy editor. Create a config view (File->New->CellView and pick your lib cell view and set the Type to be "config". Then when this opens, hit Use Template and pick "spectre". Make sure that the top cellView is pointing to your schematic and OK that form.
You'll then get a Table view showing Cell Bindings and a Tree View showing instance bindings - this is how you control which views are used for each cell or instance with greater control than just a view list and stop list which is applied everywhere.
For Ultrasim usage, use View->Properties. You'll see some additional columns appear in the table and tree view, including sim_mode and speed. You can click on these for a particular cell, or a particular instance. sim_mode is a cyclic with the various sim_mod choices (e.g. s, a, ms, da, df, dx) - and you can also set the speed.
Save your setup, and then you can hit the Open button in the hierarchy editor to open the configured schematic, From here, launch ADE (you'll see ADE shows the config as being the view being simulated) and then if Ultrasim is the simulator, it will take this information and add it to the netlist so that Ultrasim knows the per-cell or per-instance mode and speed settings.
Hope that helps,
In reply to Andrew Beckett:
Thank you very much. Found it and trying it right now.
However I'm puzzled by one simulator output. Even though I set one instance to df and one to s
the device model statistics reports only devices set to spice. Shouldn't there also be devices listed
that are set to df ? I'm using MMSIM 12.11.115
In reply to baenischfau:
I suggest you contact customer support - I don't have time to check this out myself right now.
Hi Andrew, I am currently using AMS simulator with ultrasim solver. I have a question. If I mention sim_mode and speed for a sub-block which is digital block(verilog view) then will this digital block solved by analog(ultrasim) solver, or the simulator will just ignore the sim_mode and speed option specified for this block and block will be simulated by digital solver? And for a analog block I do not mention any of sim_mode or speed, then what is the default mode the simulator will consider?
In reply to Jagdish23:
You probably should have started a new thread, but any settings for a digital block will be ignored (this doesn't influence the partitioning between the two solvers). If you don't specify the sim_mode or speed, then it will use whatever has been set on Simulation->Options->FastSPICE (UltraSim) on the Main tab.
Not sure if this was resolved, but for anyone else coming across this, there is actually a magic button that you have to set to make this work.
After you set the config view the way you like it, go back to ADE (or ADEXL) and go to Simulation->Options->FastSpice->Miscellaneous. Click "Allow usim_opt in HED." Now it should work.
Also, the option directly above allows you to specify usim_opt's on the schematic instead. For example, you can "q" schematic instances and add a user variable "usim_opt" and specifying strings like "sim_mode=s speed=1"...
For what it's worth, in simulating large mixed signal designs with Ultrasim, another critical option for me was judicious use of the "Voltage regulator" option if you have any VR's, or in my case, for power gating switches. From what I understand, this is because Ultrasim is not able to take advantage of the simplified MOS models if it doesn't see sources of devices connected to stable supplies (like vdc's or gnds), so the 1000's of digital transistors connected to a power switch (or VR) will be simulated at much higher accuracy than they need to be. When I finally realized I should apply this option, I received a very large speed-up.