Hi everyone, I am trying to perform an LVS run with a block which is streamed in from Encounter and a simple custom inverter layout which is drawn by me. My standard cell library contains cells with abstract views, therefore I need to use black box technique. I am using a simple CDL netlist for this purpose and I set related to compare rules on Assura GUI.
I managed to match the netlist and layout to certain point. The problem is, in the layout of the block which is imported from Encounter, appears two ground pins which are named as avS** and avC** and prevents the match. I call them ground pins since in the layout VNL netlist they defined so.
Any idea why this is happening and how to deal with them?
(Note: Any decent document related to this kind of flow will be highly appreciated) Best Regards! Alper
Hi AlperThis can sometimes happen for Assura blackboxes. It is due to the way the extract rules are coded. You should be able to resolve it by adding substrate and well taps in the blackbox cells.Best regardsQuek
In reply to Quek:
Hi Quek, The problem was indeed in the substrate connections. First I had tried to add substrate connections to top level layout however it didn't work. It seems that I should have put substrate taps to layout of the placed and routed block additionaly.
Thanks a lot!