hi everyone,I am laying out an analog chip with AMS 0.35um 4 metal process (c35b4) using calibre LVS/DRC verification. I am running into problems when constructing the scribe line... I used the SCRIBE_EXAMPLE cell in the SFCLIB_C35B4C3 library that came with the installation. Calibre DRC returned a large number of errors with only the SCRIBE_EXAMPLE imported. Has anyone came across the same problem before?Many Thanks in advance.
There are many variables with this problem. What type of runset did you use, was it one provided by Calibre or was it a custom runset written for you? Maybe a dropped layer or not all the layers that are needed are included in your runset file. Do the output files give you any errors or warnings? Is it all one type of error or several types of errors? Unfornuately, I do not work with Calibre but hope that these quesitons will help direct you toward a solution.Ann Votino
Thank you for the reply Ann. We have contacted the corresponding technical support team and they said it is fine for the scribe to have DRC errors as they will deal with it after our design submission. Despite we still do not know why a standard cell create errors, we are at least fine for now :-).henry