I am running LVS on a large pixel array (16-mega pixel) which contains nothing but repeating the unit pixel. The pixel array is organized in a hierarchal systems consisting of cells that group increasing number of pixels (ie 1-pixel cell, 10-pixel cell made of 10 of 1-pixel cells, 100-pixel cell made of 10 of 10-pixel cells, 1000-pixel cell made of 10 of 100-pixel cells, and so on). Both the schematic and the layout have the same structure and pins. My problem now is that when I run LVS it eats up all the memory available on the system (4 GB, the maximum memory a 32-bit system can have) and LVS stops. I thought by structuring my design in a hierarchal way the runtime and memory requirements would be minimized. Am I doing something wrong so LVS would need > 4 GB of memory? Or this is the case for everyone who need to check large array designs (such as cameral pixel arrays or memory arrays)?
It might help if you said which LVS tool you're using... since Cadence have four, it's a little hard to tell what you're doing.Andrew.
It's Assura LVS.