I have created a AND(2*1) gate symbol with PW(pmos width), PL(pmos length), NW(nmos width) and NL(nmos length) CDF parameters. And I had a schematic. I need to attach transistors widths and lengths in schematic to symbol(pmos width in schematic to PW , pmos length in schematic to PL something like that.), So that I can directly see the values on symbol from top level without entering into schematic. Let me know is there any solution.
Set the pmos transistor's width to pPar("PW"), length to pPar("PL") etc. pPar() is the function used to pass parameters.
In reply to Andrew Beckett:
Thank you Andrew, I am very greatful to you. Its working now and sorry for delay replay. Thankyou very much.
I also get another problem need your help.
I'v made pPar("PW") ...etc worked, But when I CDL out, the netlist become
.subckt inverter a x
mxp0 x a vdd vdd pmos w=pw l=pl
mxn0 x a gnd gnd nmos w=nw l=nl
I can't find where is option can make CDL out result become
.subckt inverter a x nl=2 nw=3 pl=2 pw=8
Could you help me?
Thank you very much
In reply to breezeleaf:
I think it always puts the parameter values on the instance line, not the subckt header. I'm not sure if there is an option to get the behaviour you want (I'd have to do some experiments - so you should contact customer support if you want such behaviour).