Hi there, i am looking to write a Skill procedure to identify long logic routes with high Resistance.
Purpose: to find nets that are too long and un-buffered. In our current process we know that min width routes over X microns distance will become succeptable to signal integrity issues.
Here are some things to note or that i have been thinking of:
I think to begin with i shall look for a way to identy that bits of metal are connected by given via's, if anyone knows of such functions please let me know.