Is it possible to run a veriloga script from within skill?
what Im trying to do is to run some ADE XL simulation on some schematic design, and without placing these verilogA blocks
on schematic itself, using thier verilogA syntex on results, in such a way that ADE xL will output an expression that is an outcome( output) of this verilog A block, while the inputs for this/these blocks are already expressed in ADE-XL outputs/results section.
I assume this is not possible , becuase the verilogA block wasnt part of the netlist from the begining. however this verilogA block is
proprlly defined in virtuoso data base, and contain all required view ( symbol, verilogA, aucdl).
This doesn't really fit in with how the tools work. For a start, you would generally need some stimulus for the Verilog-A model, and it would need incorporating into a circuit to simulate. So you'd normally place an instance of it in a schematic and hook it up with associated stimulus and loads and then simulate it - there's nothing to simulate it directly without a testbench.