I'd like to model a resistor in verilog ams using wreal. That is, I need the equivalent of the "tran" primitive that exists in vanilla verilog.
module res (p,n);
//need a model here, something like tran t1(p,n)
I've tried to check the inouts for the `wrealZState to determine what port is actually actually driving and set the signal direction accordingly but I couldn't get good simulation results.
Has anyone already solved this problem?
Please do not cross-post in multiple forums (the Forum Guidelines in the CIC, RF and Mixed Signal forums explicitly tell you not to do this).
It's not that obvious what you are trying to do - modelling a resistor with wreal is not really possible unless you're prepared to compromise - since you are only modelling the potential or the flow (not both) - and a resistor would normally be implemented using a conserving approach (i.e. V=I*R). So you may have to make clear what compromise you are prepared to make.
In reply to Andrew Beckett:
I appologize. I guess we should start a AMS Verification forum, everytime I want to post something I am not sure were to place it.
As for the resistor, all I needed was a wreal bidir net. Problem solved! I do have a continuous time view of that cell which is a conservative resistor model but sometimes I want to switch my system to discrete time (event driven) to speed up simulation. A bidir net does not care if the information (real number) is a potential or a flow.
In reply to freitas:
No worries. For AMS verification issues, either the Custom IC Design or Mixed Signal Design forums will be fine - take your pick! Historically the Custom IC forum is busier, but that's because it's been around longer. I'm not sure it's really worth starting another forum.
In reply to mocanu alin: