# Create Clock Tree Spec encounter 31> setCTSMode -traceDPinAsLeaf true -traceIoPinAsLeaf true -bottomPreferredLayer 6 -topPreferredLayer 8 -addClockRootProp true encounter 32> specifyClockTree -file ${top_level}.cts Checking spec file integrity... Reading clock tree spec file 'EX_EX_MEM.cts' ... RouteType : FE_CTS_DEFAULT PreferredExtraSpace : 1 Shield : NONE PreferLayer : M6 M7 M8 Est. Cap : 0.166378(V=0.173806 H=0.161677) (ff/um) [0.000166378] Est. Res : 0.2(V=0.3725 H=0.11375)(ohm/um) [0.0002] Est. Via Res : 1.8(ohm) [21.1429] Est. Via Cap : 0.348901(ff) M1(H) w=0.16(um) s=0.16(um) p=0.4(um) es=0.64(um) cap=0.164(ff/um) res=0.525(ohm/um) viaRes=0(ohm) viaCap=0(ff) M2(V) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.174(ff/um) res=0.373(ohm/um) viaRes=4(ohm) viaCap=0.190469(ff) M3(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.174(ff/um) res=0.373(ohm/um) viaRes=4.28571(ohm) viaCap=0.16884(ff) M4(V) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.174(ff/um) res=0.373(ohm/um) viaRes=4.28571(ohm) viaCap=0.16884(ff) M5(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.174(ff/um) res=0.373(ohm/um) viaRes=4.28571(ohm) viaCap=0.16884(ff) M6(V) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.174(ff/um) res=0.373(ohm/um) viaRes=4.28571(ohm) viaCap=0.16884(ff) M7(H) w=0.4(um) s=0.4(um) p=0.8(um) es=1.2(um) cap=0.162(ff/um) res=0.114(ohm/um) viaRes=1.8(ohm) viaCap=0.348901(ff) M8(V) w=0.4(um) s=0.4(um) p=0.8(um) es=1.2(um) cap=0.164(ff/um) res=0.114(ohm/um) viaRes=2.14286(ohm) viaCap=0.315807(ff) RouteType : FE_CTS_DEFAULT_LEAF PreferredExtraSpace : 1 Shield : NONE PreferLayer : M3 M4 Est. Cap : 0.173806(V=0.173806 H=0.173806) (ff/um) [0.000173806] Est. Res : 0.3725(V=0.3725 H=0.3725)(ohm/um) [0.0003725] Est. Via Res : 4.28571(ohm) [8.28571] Est. Via Cap : 0.16884(ff) M1(H) w=0.16(um) s=0.16(um) p=0.4(um) es=0.64(um) cap=0.164(ff/um) res=0.525(ohm/um) viaRes=0(ohm) viaCap=0(ff) M2(V) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.174(ff/um) res=0.373(ohm/um) viaRes=4(ohm) viaCap=0.190469(ff) M3(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.174(ff/um) res=0.373(ohm/um) viaRes=4.28571(ohm) viaCap=0.16884(ff) M4(V) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.174(ff/um) res=0.373(ohm/um) viaRes=4.28571(ohm) viaCap=0.16884(ff) M5(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.174(ff/um) res=0.373(ohm/um) viaRes=4.28571(ohm) viaCap=0.16884(ff) M6(V) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.174(ff/um) res=0.373(ohm/um) viaRes=4.28571(ohm) viaCap=0.16884(ff) M7(H) w=0.4(um) s=0.4(um) p=0.8(um) es=1.2(um) cap=0.162(ff/um) res=0.114(ohm/um) viaRes=1.8(ohm) viaCap=0.348901(ff) M8(V) w=0.4(um) s=0.4(um) p=0.8(um) es=1.2(um) cap=0.164(ff/um) res=0.114(ohm/um) viaRes=2.14286(ohm) viaCap=0.315807(ff) ****** AutoClockRootPin ****** AutoClockRootPin 1: clock # NoGating NO # SetDPinAsSync YES # SetIoPinAsSync YES # SetAsyncSRPinAsSync NO # SetTriStEnPinAsSync NO # SetBBoxPinAsSync NO # RouteClkNet NO # PostOpt YES # RouteType FE_CTS_DEFAULT # LeafRouteType FE_CTS_DEFAULT_LEAF ***** !! NOTE !! ***** CTS treats D-pins and I/O pins as non-synchronous pins by default. If you want to change the behavior, you need to use the SetDPinAsSync or SetIoPinAsSync statement in the clock tree specification file, or use the setCTSMode -traceDPinAsLeaf {true|false} command, or use the setCTSMode -traceIoPinAsLeaf {true|false} command before specifyClockTree command. *** End specifyClockTree (cpu=0:00:00.0, real=0:00:00.0, mem=890.7M) *** encounter 33> ckSynthesis -rguide ${top_level}.cts.rguide -report ${top_level}.ctsrpt -macromodel ${top_level}.ctsmdl -forceReconvergent Redoing specifyClockTree ... Checking spec file integrity... Start to trace clock trees ... *** Begin Tracer (mem=891.5M) *** Tracing Clock clock ... *** End Tracer (mem=891.5M) *** ****** Clock Tree (clock) Structure Max. Skew : 200(ps) Max. Sink Transition: 900(ps) Max. Buf Transition : 900(ps) Max. Delay : 900(ps) Min. Delay : 0(ps) Buffer : (BUFX12TR) (BUFX16TR) (BUFX20TR) (BUFX8TR) (CLKBUFX12TR) (CLKBUFX16TR) (CLKBUFX20TR) (CLKBUFX2TR) (CLKBUFX3TR) (CLKBUFX4TR) (CLKBUFX6TR) (CLKBUFX8TR) (CLKINVX1TR) (CLKINVX12TR) (CLKINVX16TR) (CLKINVX20TR) (CLKINVX2TR) (CLKINVX3TR) (INVX1TR) (CLKINVX4TR) (CLKINVX6TR) (CLKINVX8TR) (INVX12TR) (INVX16TR) (INVX20TR) (INVX2TR) (INVX3TR) (INVXLTR) (INVX4TR) (INVX6TR) (INVX8TR) Nr. Subtrees : 1 Nr. Sinks : 240 Nr. Rising Sync Pins : 240 Nr. Inverter Rising Sync Pins : 0 Nr. Falling Sync Pins : 0 Nr. Inverter Falling Sync Pins : 0 *********************************************************** ############################################################################# # # Pre-Synthesis Checks and Parameters # ############################################################################# Types of Check : Enabled|Disabled ---------------------------------------------------------------------------- Check multiple path through MUX : disabled Check gating depth : enabled Report FIXED, DontUse and DontTouch : disabled MacroModel checks : enabled Parameters of checking : CTS uses following values to determine if diagnostic checks are successful. Use setCTSMode to change default values. ---------------------------------------------------------------------------- 1) Gating depth check Maximum gating depth : 10 levels (default) 2) Macromodel check MacroModel max delay threshold : 0.9 (default) MacroModel max skew threshold : 0.9 (default) MacroModel variance step size : 100ps (default) Deep Gating Level Checks ============================================================ ** INFO Clock clock has a maximum of 0 levels of logic before synthesis. Deep Gating Level Checks Finished, CPU=0:00:00.0 ============================================================ MacroModel Debugging Check ========================== MacroModel Debugging Check Finished, CPU=0:00:00.0 ============================================================ ############################################################################# # # Summary of Pre-Synthesis Checks # ############################################################################# Types of Check : Number of warnings ---------------------------------------------------------------------------- Check multiple path through MUX : 0(disabled) Check gating depth : 0 Report FIXED, DontUse and DontTouch : 0(disabled) MacroModel checks : 0 *** End ckSynthesis (cpu=0:00:00.0, real=0:00:00.0, mem=890.7M) *** MSV CTS is analyzing clock ... Whole clock tree is inside power domain 'TOP' ** MSV CTS DontTouch net: clock Checking spec file integrity... Reading clock tree spec file '.anaMsvClk_dont_touch_nets6602.spec' ... ****** AutoClockRootPin ****** AutoClockRootPin 1: clock # NoGating NO # SetDPinAsSync YES # SetIoPinAsSync YES # SetAsyncSRPinAsSync NO # SetTriStEnPinAsSync NO # SetBBoxPinAsSync NO # RouteClkNet NO # PostOpt YES # RouteType FE_CTS_DEFAULT # LeafRouteType FE_CTS_DEFAULT_LEAF ***** !! NOTE !! ***** CTS treats D-pins and I/O pins as non-synchronous pins by default. If you want to change the behavior, you need to use the SetDPinAsSync or SetIoPinAsSync statement in the clock tree specification file, or use the setCTSMode -traceDPinAsLeaf {true|false} command, or use the setCTSMode -traceIoPinAsLeaf {true|false} command before specifyClockTree command. *** End specifyClockTree (cpu=0:00:00.0, real=0:00:00.0, mem=890.7M) *** setenv CKTDFENCEMODE1ONLY 1 setenv CK_BTS_FORCE_HINST 1 setenv CK_BTS_BUF_HINST setenv CK_MSV_CTS_NOBUF 0x7fbad746b8e8 MSV CTS Time: 0.1 seconds MSV CTS Mem: 0.0 M MSV CTS Data preparation completed. Checking spec file integrity... Skip the first phase of fence mode. ***** Allocate Placement Memory Finished (MEM: 890.465M) Start to trace clock trees ... *** Begin Tracer (mem=890.5M) *** Tracing Clock clock ... *** End Tracer (mem=890.5M) *** ***** Allocate Obstruction Memory Finished (MEM: 890.465M) ############################################################################# # # Pre-Synthesis Checks and Parameters # ############################################################################# Types of Check : Enabled|Disabled ---------------------------------------------------------------------------- Check cell drive strength : disabled Check root input transition : enabled Check pin capacitance : enabled Check multiple path through MUX : disabled Check gating depth : enabled Check placement near clock pins : enabled Check route blockages over clock pins : enabled Report FIXED, DontUse and DontTouch : disabled clock gating checks : enabled MacroModel checks : enabled Parameters of checking : CTS uses following values to determine if diagnostic checks are successful. Use setCTSMode to change default values. ---------------------------------------------------------------------------- 1) Pin capacitance check Threshold for MaxCap check : 90% of constraint (default) 2) Gating depth check Maximum gating depth : 10 levels (default) 3) Placement near clock pin check Threshold distance for placeable location : 10.8(um) (default) 4) Clock gating location check Allowed clock gate detour : 580(um) (default) Allowed clock gate sinks' BBOx overlap ratio : 0.5 (default) 5) Macromodel check MacroModel max delay threshold : 0.9 (default) MacroModel max skew threshold : 0.9 (default) MacroModel variance step size : 100ps (default) ****** Clock (clock) Diagnostic check Parameters Assumed driver input transition : 210.9(ps) (derived from BUFX20TR) Threshold for MaxBufTran check : 810(ps) derived from 90% (default) MaxBufTran constraint Threshold for MaxSinkTran check : 810(ps) derived from 90% (default) MaxSinkTran constraint Root Input Transition : [100(ps) 100(ps)] Max Cap Limit Checks ============================================================ **WARN: (ENCCK-6009): The lumped capacitance on instance pin clock of fixed net clock (timing library NULL) is 5.535pF, which may make it difficult to meet max sink transition constraint. Max Cap Limit Checks Finished, CPU=0:00:00.1 ============================================================ Deep Gating Level Checks ============================================================ ** INFO Clock clock has a maximum of 0 levels of logic before synthesis. Deep Gating Level Checks Finished, CPU=0:00:00.0 ============================================================ Max placement distance Checks ============================================================ Max placement distance Checks Finished, CPU=0:00:00.0 ============================================================ Root input tran Checks ============================================================ Root input tran Checks Finished, CPU=0:00:00.0 ============================================================ Routing OBS checks ============================================================ Routing OBS Checks Finished, CPU=0:00:00.0 ============================================================ MacroModel Debugging Check ========================== MacroModel Debugging Check Finished, CPU=0:00:00.0 ============================================================ Clock gating checks ============================================================ Clock gating Checks Finished, CPU=0:00:00.0 ============================================================ ############################################################################# # # Summary of Pre-Synthesis Checks # ############################################################################# Types of Check : Number of warnings ---------------------------------------------------------------------------- Check cell drive strength : 0(disabled) Check root input transition : 0 Check pin capacitance : 1 Check multiple path through MUX : 0(disabled) Check gating depth : 0 Check placement near clock pins : 0 Check route blockages over clock pins : 0 Report FIXED, DontUse and DontTouch : 0(disabled) clock gating checks : 0 MacroModel checks : 0 ############################################################################# # # During-Synthesis Checks and Parameters # ############################################################################# Types of Check : Enabled|Disabled ---------------------------------------------------------------------------- Check RefinePlacement move distance : enabled Check route layer follows preference : enabled Check route follows guide : enabled clock gating checks : enabled Parameters of checking : CTS uses following values to determine if diagnostic checks are successful. Use setCTSMode to change default values. ---------------------------------------------------------------------------- 1) Route layer follows preference check Minimum preferred layer utilization : 80% (default) Minimum length to check threshold : 80(um) (default) 2) Route follows guide check Deviation in length from route guide : 50% (user set) Minimum length to check threshold : 80(um) (default) Delay threshold : 10(ps) (default) 3) Saving intermediate database Save long-running subtrees time : 0(min) (default) Maximum number of saved databases : 1 (default) 4) Clock gating location check Allowed clock gate detour : 580(um) (default) ****** Clock (clock) Diagnostic check Parameters Assumed driver input transition : 210.9(ps) (derived from BUFX20TR) Threshold for MaxBufTran check : 810(ps) derived from 90% (default) MaxBufTran constraint Threshold for MaxSinkTran check : 810(ps) derived from 90% (default) MaxSinkTran constraint Movement threshold : 18.000000(um) (derived 5% of MaxBuf strength) Root Input Transition : [100(ps) 100(ps)] ****** Clock Tree (clock) Structure Max. Skew : 200(ps) Max. Sink Transition: 900(ps) Max. Buf Transition : 900(ps) Max. Delay : 900(ps) Min. Delay : 0(ps) Buffer : (BUFX12TR) (BUFX16TR) (BUFX20TR) (BUFX8TR) (CLKBUFX12TR) (CLKBUFX16TR) (CLKBUFX20TR) (CLKBUFX2TR) (CLKBUFX3TR) (CLKBUFX4TR) (CLKBUFX6TR) (CLKBUFX8TR) (CLKINVX1TR) (CLKINVX12TR) (CLKINVX16TR) (CLKINVX20TR) (CLKINVX2TR) (CLKINVX3TR) (INVX1TR) (CLKINVX4TR) (CLKINVX6TR) (CLKINVX8TR) (INVX12TR) (INVX16TR) (INVX20TR) (INVX2TR) (INVX3TR) (INVXLTR) (INVX4TR) (INVX6TR) (INVX8TR) Nr. Subtrees : 1 Nr. Sinks : 240 Nr. Rising Sync Pins : 240 Nr. Inverter Rising Sync Pins : 0 Nr. Falling Sync Pins : 0 Nr. Inverter Falling Sync Pins : 0 *********************************************************** SubTree No: 0 Input_Pin: (NULL) Output_Pin: (clock) Output_Net: (clock) DontTouch (Special PowerDomain Case) Refine place movement check ============================================================ **INFO: The distance threshold for maximum refine placement move is 18.000000 microns (5% of max driving distance). ***** Start Refine Placement..... Starting refinePlace ... **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'U234'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'U61'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'U60'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'U38'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'U22'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'U21'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'U9'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2729'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2728'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2727'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2726'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2725'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2724'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2723'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2722'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2721'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2720'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2719'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2718'. **WARN: (ENCSP-7201): Can't find side closest to preassigned shifter 'EX_MEM_pp_reg_0/U2717'. **WARN: (ENCSP-7207): Shifter 'U234' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'U61' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'U60' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'U38' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'U22' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'U21' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'U9' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2729' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2728' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2727' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2726' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2725' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2724' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2723' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2722' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2721' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2720' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2719' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2718' has no connections outside its power domain. **WARN: (ENCSP-7207): Shifter 'EX_MEM_pp_reg_0/U2717' has no connections outside its power domain. 454 shifters were already placed. 399 shifters have no external connections. move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um Spread Effort: high, pre-route mode. Finished Phase I. CPU Time = 0:00:00.2, Real Time = 0:00:00.0 move report: preRPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um move report: overall moves 0 insts, mean move: 0.00 um, max move: 0.00 um Statistics of distance of Instance movement in detailed placement: maximum (X+Y) = 0.00 um mean (X+Y) = 0.00 um Total instances moved : 0 *** cpu=0:00:00.3 mem=882.9M mem(used)=0.0M*** ***** Refine Placement Finished (CPU Time: 0:00:00.3 MEM: 882.871M) **INFO: Total instances moved beyond threshold limit during refinePlace are 0... Refine place movement check finished, CPU=0:00:00.4 ============================================================ # # Mode : Setup ********** Clock clock Pre-Route Timing Analysis ********** Nr. of Subtrees : 1 Nr. of Sinks : 240 Nr. of Buffer : 0 Nr. of Level (including gates) : 0 Root Rise Input Tran : 100(ps) Root Fall Input Tran : 100(ps) Max trig. edge delay at sink(R): EX_MEM_pp_reg_0/ex_mem_alu_result_reg_55_/CK 226.2(ps) Min trig. edge delay at sink(R): EX_MEM_pp_reg_0/ex_mem_IR_reg_29_/CK 38.4(ps) (Actual) (Required) Rise Phase Delay : 38.4~226.2(ps) 0~900(ps) Fall Phase Delay : 38.4~226.2(ps) 0~900(ps) Trig. Edge Skew : 187.8(ps) 200(ps) Rise Skew : 187.8(ps) Fall Skew : 187.8(ps) Max. Rise Buffer Tran. : 0(ps) 900(ps) Max. Fall Buffer Tran. : 0(ps) 900(ps) Max. Rise Sink Tran. : 128136(ps) 900(ps) Max. Fall Sink Tran. : 48032.1(ps) 900(ps) Min. Rise Buffer Tran. : 0(ps) 0(ps) Min. Fall Buffer Tran. : 0(ps) 0(ps) Min. Rise Sink Tran. : 128136(ps) 0(ps) Min. Fall Sink Tran. : 48032.1(ps) 0(ps) Clock Analysis (CPU Time 0:00:00.1) *** Look For Reconvergent Clock Component *** The clock tree clock has no reconvergent cell. Reducing the latency of clock tree 'clock' ... Calculating pre-route downstream delay for clock tree 'clock'... *** Look For PreservePin And Optimized CrossOver Root Pin *** MaxTriggerDelay: 226.2 (ps) MinTriggerDelay: 38.4 (ps) Skew: 187.8 (ps) *** Finished Latency Reduction ((cpu=0:00:00.1 real=0:00:00.0 mem=882.9M) *** Reducing the skew of clock tree 'clock' ... MaxTriggerDelay: 226.2 (ps) MinTriggerDelay: 38.4 (ps) Skew: 187.8 (ps) *** Finished Skew Reduction ((cpu=0:00:00.0 real=0:00:00.0 mem=882.9M) *** resized 0 standard cell(s). inserted 0 standard cell(s). deleted 0 standard cell(s). moved 0 standard cell(s). *** Optimized Clock Tree Latency (cpu=0:00:00.1 real=0:00:00.0 mem=882.9M) *** # # Mode : Setup ********** Clock clock Pre-Route Timing Analysis ********** Nr. of Subtrees : 1 Nr. of Sinks : 240 Nr. of Buffer : 0 Nr. of Level (including gates) : 0 Root Rise Input Tran : 100(ps) Root Fall Input Tran : 100(ps) Max trig. edge delay at sink(R): EX_MEM_pp_reg_0/ex_mem_alu_result_reg_55_/CK 226.2(ps) Min trig. edge delay at sink(R): EX_MEM_pp_reg_0/ex_mem_IR_reg_29_/CK 38.4(ps) (Actual) (Required) Rise Phase Delay : 38.4~226.2(ps) 0~900(ps) Fall Phase Delay : 38.4~226.2(ps) 0~900(ps) Trig. Edge Skew : 187.8(ps) 200(ps) Rise Skew : 187.8(ps) Fall Skew : 187.8(ps) Max. Rise Buffer Tran. : 0(ps) 900(ps) Max. Fall Buffer Tran. : 0(ps) 900(ps) Max. Rise Sink Tran. : 128136(ps) 900(ps) Max. Fall Sink Tran. : 48032.1(ps) 900(ps) Min. Rise Buffer Tran. : 0(ps) 0(ps) Min. Fall Buffer Tran. : 0(ps) 0(ps) Min. Rise Sink Tran. : 128136(ps) 0(ps) Min. Fall Sink Tran. : 48032.1(ps) 0(ps) Generating Clock Analysis Report EX_EX_MEM.ctsrpt .... Clock Analysis (CPU Time 0:00:00.1) *** ckSynthesis Opt Latency (cpu=0:00:00.2 real=0:00:00.0 mem=882.9M) *** # # Mode : Setup ********** Clock clock Pre-Route Timing Analysis ********** Nr. of Subtrees : 1 Nr. of Sinks : 240 Nr. of Buffer : 0 Nr. of Level (including gates) : 0 Root Rise Input Tran : 100(ps) Root Fall Input Tran : 100(ps) Max trig. edge delay at sink(R): EX_MEM_pp_reg_0/ex_mem_alu_result_reg_55_/CK 226.2(ps) Min trig. edge delay at sink(R): EX_MEM_pp_reg_0/ex_mem_IR_reg_29_/CK 38.4(ps) (Actual) (Required) Rise Phase Delay : 38.4~226.2(ps) 0~900(ps) Fall Phase Delay : 38.4~226.2(ps) 0~900(ps) Trig. Edge Skew : 187.8(ps) 200(ps) Rise Skew : 187.8(ps) Fall Skew : 187.8(ps) Max. Rise Buffer Tran. : 0(ps) 900(ps) Max. Fall Buffer Tran. : 0(ps) 900(ps) Max. Rise Sink Tran. : 128136(ps) 900(ps) Max. Fall Sink Tran. : 48032.1(ps) 900(ps) Min. Rise Buffer Tran. : 0(ps) 0(ps) Min. Fall Buffer Tran. : 0(ps) 0(ps) Min. Rise Sink Tran. : 128136(ps) 0(ps) Min. Fall Sink Tran. : 48032.1(ps) 0(ps) Clock Analysis (CPU Time 0:00:00.1) Routing correlation check ============================================================ Min length threshold value is :: 80 microns Allowed deviation from route guide is 50% Routing correlation check finished, CPU=0:00:00.0 ============================================================ # # Mode : Setup ********** Clock clock Pre-Route Timing Analysis ********** Nr. of Subtrees : 1 Nr. of Sinks : 240 Nr. of Buffer : 0 Nr. of Level (including gates) : 0 Root Rise Input Tran : 100(ps) Root Fall Input Tran : 100(ps) Max trig. edge delay at sink(R): EX_MEM_pp_reg_0/ex_mem_alu_result_reg_55_/CK 226.2(ps) Min trig. edge delay at sink(R): EX_MEM_pp_reg_0/ex_mem_IR_reg_29_/CK 38.4(ps) (Actual) (Required) Rise Phase Delay : 38.4~226.2(ps) 0~900(ps) Fall Phase Delay : 38.4~226.2(ps) 0~900(ps) Trig. Edge Skew : 187.8(ps) 200(ps) Rise Skew : 187.8(ps) Fall Skew : 187.8(ps) Max. Rise Buffer Tran. : 0(ps) 900(ps) Max. Fall Buffer Tran. : 0(ps) 900(ps) Max. Rise Sink Tran. : 128136(ps) 900(ps) Max. Fall Sink Tran. : 48032.1(ps) 900(ps) Min. Rise Buffer Tran. : 0(ps) 0(ps) Min. Fall Buffer Tran. : 0(ps) 0(ps) Min. Rise Sink Tran. : 128136(ps) 0(ps) Min. Fall Sink Tran. : 48032.1(ps) 0(ps) Clock Analysis (CPU Time 0:00:00.1) *** Non-Gated Clock Tree Optimization (cpu=0:00:00.0 real=0:00:00.0 mem=891.4M) *** *** Finished Clock Tree Skew Optimization (cpu=0:00:00.0 real=0:00:00.0 mem=891.4M) *** None of the clock tree buffers/gates are modified by the skew optimization. *** None of the buffer chains at roots are modified by the fine-tune process. *** Look For Reconvergent Clock Component *** The clock tree clock has no reconvergent cell. # # Mode : Setup ********** Clock clock Pre-Route Timing Analysis ********** Nr. of Subtrees : 1 Nr. of Sinks : 240 Nr. of Buffer : 0 Nr. of Level (including gates) : 0 Root Rise Input Tran : 100(ps) Root Fall Input Tran : 100(ps) Max trig. edge delay at sink(R): EX_MEM_pp_reg_0/ex_mem_alu_result_reg_55_/CK 226.2(ps) Min trig. edge delay at sink(R): EX_MEM_pp_reg_0/ex_mem_IR_reg_29_/CK 38.4(ps) (Actual) (Required) Rise Phase Delay : 38.4~226.2(ps) 0~900(ps) Fall Phase Delay : 38.4~226.2(ps) 0~900(ps) Trig. Edge Skew : 187.8(ps) 200(ps) Rise Skew : 187.8(ps) Fall Skew : 187.8(ps) Max. Rise Buffer Tran. : 0(ps) 900(ps) Max. Fall Buffer Tran. : 0(ps) 900(ps) Max. Rise Sink Tran. : 128136(ps) 900(ps) Max. Fall Sink Tran. : 48032.1(ps) 900(ps) Min. Rise Buffer Tran. : 0(ps) 0(ps) Min. Fall Buffer Tran. : 0(ps) 0(ps) Min. Rise Sink Tran. : 128136(ps) 0(ps) Min. Fall Sink Tran. : 48032.1(ps) 0(ps) Generating Clock Analysis Report EX_EX_MEM.ctsrpt .... Generating Clock Routing Guide EX_EX_MEM.cts.rguide .... Clock Analysis (CPU Time 0:00:00.1) Clock gating checks ============================================================ Clock gating Checks Finished, CPU=0:00:00.0 ============================================================ ############################################################################# # # Summary of During-Synthesis Checks # ############################################################################# Types of Check : Number of warnings ---------------------------------------------------------------------------- Check RefinePlacement move distance : 0 Check route layer follows preference : 0 Check route follows guide : 0 clock gating checks : 0 *** End ckSynthesis (cpu=0:00:01.3, real=0:00:01.0, mem=888.6M) *** MSV CTS finished successfully. ------------------------------------------------------------- CTS file (couldnt attach more than one file on the forums) ------------------------------------------------------------- ############################################################### # Generated by: Cadence Encounter 10.10-s002_1 # OS: Linux x86_64(Host ID eecs2331p03.engin.umich.edu) # Generated on: Mon Apr 22 11:21:23 2013 # Design: EX_EX_MEM # Command: createClockTreeSpec -output EX_EX_MEM.cts ############################################################### # # Encounter(R) Clock Synthesis Technology File Format # #-- MacroModel -- #MacroModel pin #-- Special Route Type -- #RouteTypeName specialRoute #TopPreferredLayer 8 #BottomPreferredLayer 6 #PreferredExtraSpace 1 #End #-- Regular Route Type -- #RouteTypeName regularRoute #TopPreferredLayer 4 #BottomPreferredLayer 3 #PreferredExtraSpace 1 #End #-- Clock Group -- #ClkGroup #+ #------------------------------------------------------------ # Clock Root : clock # Clock Name : clock # Clock Period : 38ns #------------------------------------------------------------ AutoCTSRootPin clock Period 38ns MaxDelay 0.9ns # sdc driven default MinDelay 0ns # sdc driven default MaxSkew 200ps # set_clock_uncertainty SinkMaxTran 900ps # set_clock_transition BufMaxTran 900ps # set_clock_transition Buffer BUFX12TR BUFX16TR BUFX20TR BUFX8TR CLKBUFX12TR CLKBUFX16TR CLKBUFX20TR CLKBUFX2TR CLKBUFX3TR CLKBUFX4TR CLKBUFX6TR CLKBUFX8TR CLKINVX1TR CLKINVX12TR CLKINVX16TR CLKINVX20TR CLKINVX2TR CLKINVX3TR INVX1TR CLKINVX4TR CLKINVX6TR CLKINVX8TR INVX12TR INVX16TR INVX20TR INVX2TR INVX3TR INVXLTR INVX4TR INVX6TR INVX8TR NoGating NO DetailReport YES #SetDPinAsSync YES #SetIoPinAsSync YES #SetASyncSRPinAsSync NO #SetTriStEnPinAsSync NO #SetBBoxPinAsSync NO #RouteClkNet YES #PostOpt YES #OptAddBuffer YES #RouteType specialRoute #LeafRouteType regularRoute END