VERSION 5.6 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;

PROPERTYDEFINITIONS
  LIBRARY hiResSub STRING "NO" ;
  LIBRARY supplySpec STRING "ANY" ;
  LIBRARY TopMetal STRING "M6" ;
  LIBRARY TECH STRING "cmrf7sf" ;
END PROPERTYDEFINITIONS

UNITS
  DATABASE MICRONS 1000 ;
END UNITS
MANUFACTURINGGRID 0.01 ;
LAYER RX
  TYPE MASTERSLICE ;
END RX

LAYER PC
  TYPE MASTERSLICE ;
END PC

LAYER CA
  TYPE CUT ;
  SPACING 0.24 ;
  WIDTH 0.2 ;
END CA

LAYER M1
  TYPE ROUTING ;
  DIRECTION HORIZONTAL ;
  PITCH 0.44 0.44 ;
  WIDTH 0.24 ;
  OFFSET 0.22 0.2 ;
  SPACING 0.2 ;
  RESISTANCE RPERSQ 0.071 ;
END M1

LAYER V1
  TYPE CUT ;
  SPACING 0.28 ;
  WIDTH 0.28 ;
END V1

LAYER M2
  TYPE ROUTING ;
  DIRECTION VERTICAL ;
  PITCH 0.56 0.56 ;
  WIDTH 0.28 ;
  SPACING 0.28 ;
  RESISTANCE RPERSQ 0.089 ;
END M2

LAYER V2
  TYPE CUT ;
  SPACING 0.28 ;
  WIDTH 0.28 ;
END V2

LAYER M3
  TYPE ROUTING ;
  DIRECTION HORIZONTAL ;
  PITCH 0.56 0.56 ;
  WIDTH 0.28 ;
  SPACING 0.28 ;
  RESISTANCE RPERSQ 0.089 ;
END M3

LAYER V3
  TYPE CUT ;
  SPACING 0.28 ;
  WIDTH 0.28 ;
END V3

LAYER M4
  TYPE ROUTING ;
  DIRECTION VERTICAL ;
  PITCH 0.56 0.56 ;
  WIDTH 0.28 ;
  SPACING 0.28 ;
  RESISTANCE RPERSQ 0.089 ;
END M4

LAYER V4
  TYPE CUT ;
  SPACING 0.28 ;
  WIDTH 0.28 ;
END V4

LAYER MT
  TYPE ROUTING ;
  DIRECTION HORIZONTAL ;
  PITCH 0.56 0.56 ;
  WIDTH 0.28 ;
  SPACING 0.28 ;
  RESISTANCE RPERSQ 0.089 ;
END MT

LAYER FT
  TYPE CUT ;
  SPACING 2 ;
  WIDTH 1.24 ;
END FT

LAYER ML
  TYPE ROUTING ;
  DIRECTION VERTICAL ;
  PITCH 4.8 4.8 ;
  WIDTH 2.4 ;
  SPACING 2.4 ;
  RESISTANCE RPERSQ 0.014 ;
END ML

LAYER OVERLAP
  TYPE OVERLAP ;
END OVERLAP

VIARULE PC_M1 GENERATE DEFAULT
  LAYER PC ;
    ENCLOSURE 0.06 0.06 ;
  LAYER M1 ;
    ENCLOSURE 0.02 0.02 ;
  LAYER CA ;
    RECT -0.1 -0.1 0.1 0.1 ;
    SPACING 0.44 BY 0.44 ;
    RESISTANCE 5.000000 ;
END PC_M1

VIARULE RX_M1 GENERATE DEFAULT
  LAYER RX ;
    ENCLOSURE 0.2 0.2 ;
  LAYER M1 ;
    ENCLOSURE 0.02 0.02 ;
  LAYER CA ;
    RECT -0.1 -0.1 0.1 0.1 ;
    SPACING 0.44 BY 0.44 ;
    RESISTANCE 5.000000 ;
END RX_M1

VIARULE DPC_M1 GENERATE DEFAULT
  LAYER PC ;
    ENCLOSURE 0.06 0.06 ;
  LAYER M1 ;
    ENCLOSURE 0.02 0.02 ;
  LAYER CA ;
    RECT -0.1 -0.1 0.1 0.1 ;
    SPACING 0.44 BY 0.44 ;
    RESISTANCE 5.000000 ;
END DPC_M1

VIARULE DRX_M1 GENERATE DEFAULT
  LAYER RX ;
    ENCLOSURE 0.2 0.2 ;
  LAYER M1 ;
    ENCLOSURE 0.02 0.02 ;
  LAYER CA ;
    RECT -0.1 -0.1 0.1 0.1 ;
    SPACING 0.44 BY 0.44 ;
    RESISTANCE 5.000000 ;
END DRX_M1

VIARULE M1_M2 GENERATE DEFAULT
  LAYER M1 ;
    ENCLOSURE -0.02 -0.02 ;
  LAYER M2 ;
    ENCLOSURE 0 0 ;
  LAYER V1 ;
    RECT -0.14 -0.14 0.14 0.14 ;
    SPACING 0.56 BY 0.56 ;
    RESISTANCE 5.000000 ;
END M1_M2

VIARULE DM1_M2 GENERATE DEFAULT
  LAYER M1 ;
    ENCLOSURE -0.02 -0.02 ;
  LAYER M2 ;
    ENCLOSURE 0 0 ;
  LAYER V1 ;
    RECT -0.14 -0.14 0.14 0.14 ;
    SPACING 0.56 BY 0.56 ;
    RESISTANCE 5.000000 ;
END DM1_M2

VIARULE M2_M3 GENERATE DEFAULT
  LAYER M2 ;
    ENCLOSURE 0 0 ;
  LAYER M3 ;
    ENCLOSURE 0 0 ;
  LAYER V2 ;
    RECT -0.14 -0.14 0.14 0.14 ;
    SPACING 0.56 BY 0.56 ;
    RESISTANCE 5.000000 ;
END M2_M3

VIARULE DM2_M3 GENERATE DEFAULT
  LAYER M2 ;
    ENCLOSURE 0 0 ;
  LAYER M3 ;
    ENCLOSURE 0 0 ;
  LAYER V2 ;
    RECT -0.14 -0.14 0.14 0.14 ;
    SPACING 0.56 BY 0.56 ;
    RESISTANCE 5.000000 ;
END DM2_M3

VIARULE M3_M4 GENERATE DEFAULT
  LAYER M3 ;
    ENCLOSURE 0 0 ;
  LAYER M4 ;
    ENCLOSURE 0 0 ;
  LAYER V3 ;
    RECT -0.14 -0.14 0.14 0.14 ;
    SPACING 0.56 BY 0.56 ;
    RESISTANCE 5.000000 ;
END M3_M4

VIARULE DM3_M4 GENERATE DEFAULT
  LAYER M3 ;
    ENCLOSURE 0 0 ;
  LAYER M4 ;
    ENCLOSURE 0 0 ;
  LAYER V3 ;
    RECT -0.14 -0.14 0.14 0.14 ;
    SPACING 0.56 BY 0.56 ;
    RESISTANCE 5.000000 ;
END DM3_M4

VIARULE M4_MT GENERATE DEFAULT
  LAYER M4 ;
    ENCLOSURE 0 0 ;
  LAYER MT ;
    ENCLOSURE 0 0 ;
  LAYER V4 ;
    RECT -0.14 -0.14 0.14 0.14 ;
    SPACING 0.56 BY 0.56 ;
    RESISTANCE 5.000000 ;
END M4_MT

VIARULE DM4_MT GENERATE DEFAULT
  LAYER M4 ;
    ENCLOSURE 0 0 ;
  LAYER MT ;
    ENCLOSURE 0 0 ;
  LAYER V4 ;
    RECT -0.14 -0.14 0.14 0.14 ;
    SPACING 0.56 BY 0.56 ;
    RESISTANCE 5.000000 ;
END DM4_MT

VIARULE MT_ML GENERATE DEFAULT
  LAYER MT ;
    ENCLOSURE 1 1 ;
  LAYER ML ;
    ENCLOSURE 0.6 0.6 ;
  LAYER FT ;
    RECT -0.62 -0.62 0.62 0.62 ;
    SPACING 3.24 BY 3.24 ;
    RESISTANCE 5.000000 ;
END MT_ML

VIARULE DMT_ML GENERATE DEFAULT
  LAYER MT ;
    ENCLOSURE 1 1 ;
  LAYER ML ;
    ENCLOSURE 0.6 0.6 ;
  LAYER FT ;
    RECT -0.62 -0.62 0.62 0.62 ;
    SPACING 3.24 BY 3.24 ;
    RESISTANCE 5.000000 ;
END DMT_ML

SPACING
  SAMENET RX RX 0.26 ;
  SAMENET PC PC 0.24 ;
  SAMENET M1 M1 0.2 ;
  SAMENET M2 M2 0.28 ;
  SAMENET M3 M3 0.28 ;
  SAMENET M4 M4 0.28 ;
  SAMENET MT MT 0.28 ;
  SAMENET ML ML 2.4 ;
END SPACING

SITE CoreSite
  CLASS CORE ;
  SIZE 0.56 BY 41.36 ;
END CoreSite

MACRO NAND2
  CLASS CORE ;
  ORIGIN -9.98 17.18 ;
  FOREIGN NAND2 9.98 -17.18 ;
  SIZE 2.64 BY 41.5 ;
  SYMMETRY X ;
  SITE CoreSite ;
  PIN IN2
    DIRECTION INPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        RECT 10 -0.75 10.82 -0.51 ;
    END
  END IN2
  PIN IN1
    DIRECTION INPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        RECT 10 -1.31 11.58 -1.07 ;
    END
  END IN1
  PIN OUT
    DIRECTION OUTPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        RECT 10.48 -0.24 10.72 23.4 ;
        RECT 10.48 -0.24 12.12 0 ;
        RECT 11.88 -15.72 12.12 23.4 ;
    END
  END OUT
  PIN VDD
    DIRECTION INOUT ;
    USE POWER ;
    PORT
      LAYER M1 ;
        RECT 11.18 0.44 11.42 24.31 ;
        RECT 10.06 23.93 12.12 24.31 ;
    END
  END VDD
  PIN VSS
    DIRECTION INOUT ;
    USE GROUND ;
    PORT
      LAYER M1 ;
        RECT 10.48 -16.96 10.72 -1.76 ;
        RECT 10.48 -16.96 11.48 -16.72 ;
    END
  END VSS
  OBS
    LAYER M1 ;
      RECT 10 -0.75 10.82 -0.51 ;
      RECT 11.18 -15.72 11.42 -1.76 ;
      RECT 10.48 -16.96 11.48 -16.72 ;
      RECT 10.48 -16.96 10.72 -1.76 ;
      RECT 10 -1.31 11.58 -1.07 ;
      RECT 11.18 0.44 11.42 24.31 ;
      RECT 10.06 23.93 12.12 24.31 ;
      RECT 10.48 -0.24 12.12 0 ;
      RECT 10.48 -0.24 10.72 23.4 ;
      RECT 11.88 -15.72 12.12 23.4 ;
  END
END NAND2

MACRO NAND3
  CLASS CORE ;
  ORIGIN -0.27 23.81 ;
  FOREIGN NAND3 0.27 -23.81 ;
  SIZE 3.34 BY 45.14 ;
  SYMMETRY X ;
  SITE CoreSite ;
  PIN IN1
    DIRECTION INPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        RECT 0.29 -1.92 2.57 -1.68 ;
    END
  END IN1
  PIN IN2
    DIRECTION INPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        RECT 0.29 -1.3 1.87 -1.06 ;
    END
  END IN2
  PIN IN3
    DIRECTION INPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        RECT 0.29 -0.74 1.11 -0.5 ;
    END
  END IN3
  PIN VSS
    DIRECTION INOUT ;
    USE GROUND ;
    PORT
      LAYER M1 ;
        RECT 0.77 -23.59 1.01 -2.39 ;
        RECT 0.77 -23.59 1.77 -23.35 ;
    END
  END VSS
  PIN VDD
    DIRECTION INOUT ;
    USE POWER ;
    PORT
      LAYER M1 ;
        RECT 0.77 0.45 1.01 21.32 ;
        RECT 2.17 0.45 2.41 21.32 ;
        RECT 0.35 20.94 2.69 21.32 ;
    END
  END VDD
  PIN OUT
    DIRECTION OUTPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        RECT 1.47 -0.24 1.71 20.41 ;
        RECT 1.47 -0.24 3.11 0 ;
        RECT 2.87 -22.35 3.11 20.41 ;
    END
  END OUT
  OBS
    LAYER M1 ;
      RECT 0.29 -0.74 1.11 -0.5 ;
      RECT 1.47 -22.35 1.71 -2.39 ;
      RECT 0.77 -23.59 1.77 -23.35 ;
      RECT 0.77 -23.59 1.01 -2.39 ;
      RECT 0.29 -1.3 1.87 -1.06 ;
      RECT 2.17 -22.35 2.41 -2.39 ;
      RECT 0.29 -1.92 2.57 -1.68 ;
      RECT 0.77 0.45 1.01 21.32 ;
      RECT 2.17 0.45 2.41 21.32 ;
      RECT 0.35 20.94 2.69 21.32 ;
      RECT 1.47 -0.24 3.11 0 ;
      RECT 1.47 -0.24 1.71 20.41 ;
      RECT 2.87 -22.35 3.11 20.41 ;
  END
END NAND3

MACRO NOT
  CLASS CORE ;
  ORIGIN -0.18 32.13 ;
  FOREIGN NOT 0.18 -32.13 ;
  SIZE 1.94 BY 83.46 ;
  SYMMETRY X ;
  SITE CoreSite ;
  PIN IN
    DIRECTION INPUT ;
    USE ANALOG ;
    PORT
      LAYER M1 ;
        RECT 0.28 -0.45 1.02 -0.21 ;
    END
  END IN
  PIN OUT
    DIRECTION OUTPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        RECT 1.38 -30.67 1.62 50.41 ;
    END
  END OUT
  PIN VDD
    DIRECTION INOUT ;
    USE POWER ;
    PORT
      LAYER M1 ;
        RECT 0.68 0.45 0.92 51.32 ;
        RECT 0.26 50.94 1.2 51.32 ;
    END
  END VDD
  PIN VSS
    DIRECTION INOUT ;
    USE GROUND ;
    PORT
      LAYER M1 ;
        RECT 0.68 -31.91 0.92 -0.71 ;
        RECT 0.68 -31.91 1.54 -31.67 ;
    END
  END VSS
  OBS
    LAYER M1 ;
      RECT 0.28 -0.45 1.02 -0.21 ;
      RECT 0.68 0.45 0.92 51.32 ;
      RECT 0.26 50.94 1.2 51.32 ;
      RECT 0.68 -31.91 1.54 -31.67 ;
      RECT 0.68 -31.91 0.92 -0.71 ;
      RECT 1.38 -30.67 1.62 50.41 ;
  END
END NOT

END LIBRARY