/*--------------------------------------------------------------------------*/
/* Module      : clock_divider                                              */
/*                                                                          */
/* File Name   : clock_divider.v                                            */
/* Version     : 1.0 beta 1                                                 */
/* Date        : June 5 , 2007                                              */
/* Author      : Amir Attarha                                               */
/* Copyright   : Cadence Design Systems, Inc.                               */
/* Code Type   : RTL with assertions in  PSL                                */
/* Description : This block creates a divided version of an input clock     */
/*               based on the divided reatio. If the divided ratio          */
/*               changes the new clock ratio  appears after finishing       */
/*               current activity.                                          */
/* Technology  : Formal + Siumlation + Emulation                            */
/*--------------------------------------------------------------------------*/
/*##########################################################################*/
/*                                                                          */
/* (c) Copyright 2004, Cadence Design Systems, Inc.                         */
/* All rights reserved.                                                     */
/*                                                                          */
/* This software is the proprietary information of Cadence Design           */
/* Systems, Inc. and may not be copied or reproduced in whole or in part    */
/* onto any medium without Cadence's express prior written consent.         */
/*                                                                          */
/* This software is provided to the end user solely for his/her use.  No    */
/* warranties are expressed or implied herein including those as to         */
/* merchantability and fitness for a particular purpose.  In no event       */
/* shall Cadence be held liable for loss of profit, business                */
/* interruption, data, loss of information, or any other pecuniary loss     */
/* including but not limited to special, incidental, consequential, or      */
/* other damages.                                                           */
/*                                                                          */
/*##############     USAGE          ########################################*/
/* use compiler directive +define+ABV_ON to activate assertions             */  
/*##########################################################################*/

module clock_divider ( rst_n, 
                       clk, 
                       division_ratio,
                       outclk);
parameter WIDTH = 8;
input rst_n, clk;
input [WIDTH-1:0] division_ratio;
output outclk;
reg outclk;

reg [WIDTH-1:0] division_ratio_stable;
reg [WIDTH-1:0] divclk_counter;
reg [1:0] outclk_counter;
reg completed;
reg start_up;
always @ (posedge clk or negedge rst_n)
  if (!rst_n)
    start_up <= 1'b1;
  else 
    start_up <= 1'b0 ;

always @ (posedge clk or negedge rst_n)
  if (!rst_n)
      division_ratio_stable <= {WIDTH{1'b0}};
  else if (completed || start_up)
      division_ratio_stable <= division_ratio;


always @ (posedge clk or negedge rst_n)
  if (!rst_n)
  begin        
      divclk_counter <= {WIDTH{1'b0}};
      outclk <= 1'b0;
  end
  else if (divclk_counter == (division_ratio_stable - {{(WIDTH-2){1'b0}},1'b1}) )
  begin          
      divclk_counter <= {WIDTH{1'b0}};
      outclk <= !outclk;
  end
  else    
      divclk_counter <= divclk_counter + {{(WIDTH-2){1'b0}},1'b1};

always @(*)
if ((divclk_counter == (division_ratio_stable - {{(WIDTH-2){1'b0}},1'b1}) ) && !outclk)
    completed = 1'b1;
else 
    completed = 1'b0;
`ifdef ABV_ON

generate 
genvar i;
for (i=0; i<256; i=i+1) begin: u0
 vcomp_clkdivider #(.WIDTH(8), .RATIO(i)) vcomp_clkdivider (
                              .clk(clk) , 
                              .rst_n(rst_n), 
                              .division_ratio_stable(division_ratio_stable),
                              .outclk(outclk));
end
endgenerate
`endif

endmodule

module vcomp_clkdivider (clk, rst_n, division_ratio_stable, outclk );
parameter WIDTH = 8;
parameter RATIO = 4;
input rst_n, clk;
input [WIDTH-1:0] division_ratio_stable;
input outclk;
//psl default clock =  (posedge clk);
// psl assert_div_by_n: assert always ( {division_ratio_stable==RATIO && rose(outclk)} |-> {
//               outclk[*RATIO];!outclk[*RATIO];outclk}) abort(!rst_n);
endmodule
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