ncvlog: 06.20-p001: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
import sn_params_packer::*;
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ncvlog: *E,MULTPK (specman.sv,142|22): Multiple (2) packages named "sn_params_packer" were found in the searched libraries: 
		-> found verilog_package worklib.sn_params_packer:verilog_package (VST)
		-> found verilog_package worklib.sn_params_packer:ncrunsv (VST).
import sn_params_packer::*;
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ncvlog: *E,NOPBIND (specman.sv,142|22): Package sn_params_packer could not be bound.
  specman_types::sn_dut_instruction arg_0_of_port_1;
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ncvlog: *E,NOSYM (specman.sv,178|34): sn_dut_instruction could not be found in package specman_types.
  specman_types::sn_dut_instruction arg_0_of_port_1;
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ncvlog: *E,SVNOTY (specman.sv,178|14): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
    static sv_sn_intf intf;
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ncvlog: *E,NOIPRT (specman.sv,180|20): Unrecognized declaration 'sv_sn_intf' could be a spelling mistake [SystemVerilog].
    static sv_sn_intf intf;
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ncvlog: *E,NOTINF (specman.sv,180|20): Interfaces are not allowed within tasks [SystemVerilog].
    static sv_sn_intf intf;
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ncvlog: *E,ILLPDL (specman.sv,180|25): Mixing of ansi & non-ansi style port declaration is not legal.
    params_int_array_1 = new[param_size];
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ncvlog: *E,EXPRPA (specman.sv,181|21): expecting a right parenthesis (')') [A.2.6(IEEE)].
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