Hi all . I was trying to simulate a hspice 22fdsoi netlist using spectre. Please check my sulimulation file as *****
simulator lang=spice
.title t9_inx1_cnl : 4 structure with 21 stages , analysis at 6
.option numdgt=10 measdgt=10 autostop=0 post=0 probe=1 measform=1 brief=1
*redefmodel=1 USE_TEMP = LAST
.param in_tran='1p*1.66'
.param timing=1
.param leakage=0
.param internal=0
.param vdd_v=0.72v
.inc '/proj/char_vol1/GF14LPP/users/nkala/Simulations/22fdsoi/spice_netlists/nominal/t9_inx1_cnl.sp'
****************fo4 structure***************
.SUBCKT t9_inx1_cnl_FO4 A VSS VDD Z
X0 VSS A VDD Z VSS VDD t9_inx1_cnl
X1 VSS A VDD tmp_Z_1 VSS VDD t9_inx1_cnl
X2 VSS A VDD tmp_Z_2 VSS VDD t9_inx1_cnl
X3 VSS A VDD tmp_Z_3 VSS VDD t9_inx1_cnl
C_OUT_Z_1 tmp_Z_1 0 3f
C_OUT_Z_2 tmp_Z_2 0 3f
C_OUT_Z_3 tmp_Z_3 0 3f
.ENDS
****************fo4 Structure of Analysis stage*************************
.SUBCKT t9_inx1_cnl_FO4_analysis A VSS VDD VSS1 VDD1 Z
X0 VSS1 A VDD1 Z VSS VDD t9_inx1_cnl
**********************Stages Structure***************
X_TOP VSS A VDD Z1 VSS VDD t9_inx1_cnl
X1 Z1 VSS VDD Z2 t9_inx1_cnl_FO4
X2 Z2 VSS VDD Z3 t9_inx1_cnl_FO4
X3 Z3 VSS VDD Z4 t9_inx1_cnl_FO4
X4 Z4 VSS VDD Z5 t9_inx1_cnl_FO4
X5 Z5 VSS VDD Z6 t9_inx1_cnl_FO4
X6 Z6 VSS VDD VSS1 VDD1 Z7 t9_inx1_cnl_FO4_analysis
X7 Z7 VSS VDD Z8 t9_inx1_cnl_FO4
X8 Z8 VSS VDD Z9 t9_inx1_cnl_FO4
X9 Z9 VSS VDD Z10 t9_inx1_cnl_FO4
X10 Z10 VSS VDD Z11 t9_inx1_cnl_FO4
X11 Z11 VSS VDD Z12 t9_inx1_cnl_FO4
X12 Z12 VSS VDD Z13 t9_inx1_cnl_FO4
X13 Z13 VSS VDD Z14 t9_inx1_cnl_FO4
X14 Z14 VSS VDD Z15 t9_inx1_cnl_FO4
X15 Z15 VSS VDD Z16 t9_inx1_cnl_FO4
X16 Z16 VSS VDD Z17 t9_inx1_cnl_FO4
X17 Z17 VSS VDD Z18 t9_inx1_cnl_FO4
X18 Z18 VSS VDD Z19 t9_inx1_cnl_FO4
X19 Z19 VSS VDD Z20 t9_inx1_cnl_FO4
X20 Z20 VSS VDD Z21 t9_inx1_cnl_FO4
X21 Z21 VSS VDD Z22 t9_inx1_cnl_FO4
***********************timing measurement*****************
.if(timing==1)
simulator lang=spectre
include "/proj/PDK/22fdsoi/default/Spectre/models/design_wrapper.lib.scs" section=SS_pre
.temp -40
X_CAP VSS in_cap VDD Zcap VSS VDD t9_inx1_cnl
I_in 0 in_cap 0.5u
.IC V(in_cap) = 0
.meas tran input_tran trig V(in_cap) val='vdd_v*0.3' rise=1 targ V(in_cap) val='vdd_v*0.7' rise=1 print=0
.meas tran input_cap param='(input_tran*0.5e-06)/(vdd_v*0.6)';
.meas tran rise_delay trig V(Z6) val = 'vdd_v/2' fall = 1 targ V(Z7) val = 'vdd_v/2' rise = 1
.meas tran fall_delay trig V(Z6) val = 'vdd_v/2' rise = 1 targ V(Z7) val = 'vdd_v/2' fall = 1
.meas tran rise_tran trig V(Z7) val = 'vdd_v * 0.3' rise = 1 targ V(Z7) val = 'vdd_v * 0.7' rise = 1
.meas tran fall_tran trig V(Z7) val = 'vdd_v * 0.7' fall = 1 targ V(Z7) val = 'vdd_v * 0.3' fall = 1
*******************leakage measurement**************
.elseif(leakage==1)
include "/proj/PDK/22fdsoi/default/Spectre/models/design_wrapper.lib.scs" section=FF_pre
.temp 125
.meas tran current_avg_0 avg I(V_VDD1) from = 6n to = 10n print=0
.meas tran current_avg_1 avg I(V_VDD1) from = 11n to = 15n print=0
.meas tran leakage_0 param = 'abs(current_avg_0) * vdd_v'
.meas tran leakage_1 param = 'abs(current_avg_1) * vdd_v'
*******************internal energy measurement**************
.elseif(internal==1)
.meas tran leakage_0 param = 'abs(current_avg_0) * vdd_v' print=0
.meas tran leakage_1 param = 'abs(current_avg_1) * vdd_v'print=0
.meas tran integ_current_rise integ I(V_VDD1) from=10n to=12n print=0
.meas tran internal_pow_rise param = 'abs(integ_current_rise * vdd_v)-(leakage_1 * 2n)-(input_cap*4*vdd_v*vdd_v)'
.meas tran integ_current_fall integ I(V_VDD1) from=5n to=7n print=0
.meas tran internal_pow_fall param = 'abs(integ_current_fall * vdd_v)-(leakage_0 * 2n)'
.meas tran input_cap param='(input_tran*0.5e-06)/(vdd_v*0.6)' print=0;
.endif
*******************Input Stimuli and Simulation***************
V_VDD VDD 0 vdd_v
V_VSS VSS 0 0
V_VDD1 VDD1 0 vdd_v
V_VSS1 VSS1 0 0
V_A A 0 pwl
+ 0 0
+ 5n 0
+ '5n + ( in_tran * 1.66 )' vdd_v
+ 10n vdd_v
+ '10n + ( in_tran * 1.66)' 0
.tran 1p 15n
*.probe V(A) V(Z6) V(Z7)
.alter leakage_power
.param timing=0 leakage=1
.param vdd_v=0.88
.alter internal_power
.param timing=0 leakage=0 internal=1
.param vdd_v=0.88v
.end
Best Regards,
Nitin