In some tools (eg Hspice), a common technique to help convergence of transient sims of mixed logic + analog is to "buffer" PULSE sources (for incoming logic signals) thru a piecewise-linear voltage-controlled voltage-source ("PWL" similar to DC TABLE) that forces linear interpolation of the rise/fall, *and* it forces all the derivatives (dV/dt) to be continuous as well. In countless cases this has helped TRAN sims converge where nothing else helped. Regrettably, this technique appears to have no effect in Pspice.
Is there a preferred/recommended approach that accomplishes the same effect (continuous derivatives) for Pspice short of introducing series low-pass (RC) filters on all the logic signals? RC-filters also introduce significant delay, which is objectionable.
PSpice adoptive timestep algo should take care of such transition. There are no global option to dynamically modify voltage sources. At global level one can play with GMIN (increase that) or force maximum time step to make things linear (or piece wise linear). If you are using digital GATE models of PSpice you can also try setting DIGITAL simulation related options. Some of the option, which may be relevant in this case DIGFREQ minimum digital time step is 1/DIGFREQDIGDRVF minimum drive resistanceAdditional details for various options can be found in "PSpice A/D Reference Guide"