Cadence Community

Clipped Voronoi Meshing: Deterministic Grids for Industrial-Scale LES

AnneMarie S — Fri, 16 Oct 2026 19:00:00 GMT

How clipped Voronoi diagram meshing removes the inflation layer step, makes mesh topology reproducible across teams, and brings wall-modeled LES turnaround inside a design cycle. (read more)

When AI Moves the World: Building a Chiplet Standard for Physical AI

Mick Posner — Fri, 16 Oct 2026 13:00:00 GMT

Introducing a new OCP FCSA sub-project workstream for real-time, safety-critical physical AI systems

Most AI systems return an answer. Physical AI systems must return a motion: a steering correction, a robotic arm trajectory, or an emergency stop. The output is not a prediction on a screen. It is a force applied to the world, on a deadline, often with people nearby.

That difference changes what the silicon underneath must guarantee. If that silicon is no longer one monolithic die but a package of potentially independently sourced chiplets, those guarantees stop being any single supplier's problem to solve.

To address this, a new physical AI sub-project workstream is being introduced under the Open Compute Project's Foundation Chiplet System Architecture (OCP FCSA). Its purpose is to extend the data center, cloud, and server-centric FCSA baseline with the specification requirements to satisfy real-time, safety-critical physical systems, while retaining everything FCSA already defines.

What Makes Physical AI Different

A physical AI system must perceive, reason, and act safely within real-world boundary conditions to address the determinism and criticality required in physical world interaction. Because decisions directly affect physical behavior, six constraints apply to every design.

Perceiving and Reacting

Sensor fusion: One-time-valid view of the environment from camera, radar, and lidar
Deterministic timing: Bounded, repeatable latency from sensing to action, worst case. and not just average

Acting Safely

Reliability and safety: Detect faults, report them, and reach a safe state within the deadline
Security and trust: No untrusted actor can command physical motion or alter safety behavior

Across the Whole Platform

Power and thermal efficiency: Sustain performance inside a fixed power envelope
Multi-chiplet scalability: One architecture that grows across product tiers and suppliers

Figure 1. Physical AI constraints

Why Chiplets Matter, and What They Complicate

Chiplets are compelling for physical AI for four reasons: scalable composition of compute (Including CPU and AI scaling), sensor, memory, safety, security, and I/O across product tiers; function partitioning, where sensor, AI, memory, safety, and actuator functions can span several dies; independent sourcing from different suppliers on different update schedules; and reuse, letting one architecture scale from entry-level to high-end products.

That flexibility is genuinely needed. Physical AI platforms do not share a single architectural profile. Preliminary comparison across representative categories, including vehicles, robots, drones, and other autonomous machines, suggests very different centers of gravity: high AI throughput and sensor ingress in one case, deterministic control and industrial connectivity in another, compact perception under strict size, weight, and power limits in a third.

The same functional partitioning that enables this introduces five new concerns.

Latency and jitter uncertainty: No longer fixed by a single design
Distributed trust boundaries: The security perimeter now spans chiplets and suppliers
Cross-chiplet fault propagation: One die can disturb another die's control path
Lifecycle and configuration complexity: Discovery, update, and configuration go package-wide
Observability and evidence gaps: No single die can evidence the whole package

Each of these crosses a chiplet boundary, which makes them a standardization concern.

A Physical AI Profile for OCP FCSA

The workstream is proposed as a sub-project under OCP FCSA rather than as a standalone effort, for four reasons. FCSA already owns the chiplet system architecture baseline that physical AI builds on. Real-time and safety-critical concerns go beyond that baseline's current scope. OCP FCSA is the right place to standardize externally visible chiplet behavior. Finally, OCP FCSA delivers a concrete starting point to work from.

OCP FCSA rules will be retained, and requirement rules specific to physical AI, such as real-time, secure, reliable, and safety-critical physical systems are added. In practice, that means following the OCP FCSA chapter structure wherever possible, adopting the same rules-based writing model, and applying a strict anti-duplication discipline, especially where an OCP FCSA rule already satisfies a physical AI requirement, reference it rather than restate it. Where a proposed requirement conflicts with the baseline, the conflict is named explicitly and resolved through the OCP FCSA working group.

Each candidate is then classified by interoperability impact: baseline OCP FCSA reuse, required physical AI profile, optional profile, or architecture-specific guidance. Classifying candidates this way lets the group standardize what must interoperate across chiplets and leave the rest as guidance.

Figure 2. Driving standardization via OCP FCSA

From Constraints to Architecture

An initial six constraints describe what a physical AI platform must guarantee.

Figure 3. The initial six physical AI platform constraints, starting point of the new profile

However, these initial six constraints are not directly specifiable. The bridging step maps each one to an architecture requirement area that can actually hold rules.

Physical AI constraint	Architecture areas it drives
Deterministic timing	Closed-loop control; deterministic execution; real-time interconnect
Security and trust	Security for physical action
Power and thermal efficiency	Energy efficiency and power management; heterogeneous compute
Reliability and safety	Functional safety; safety management and observability
Sensor fusion	Sensor fusion and perception data
Multi-chiplet scalability	Multi-chiplet scalability

These initial six constraints, ten areas, and every candidate requirement trace back to a constraint. That traceability is what keeps the supplement from accumulating interface features with no system-level justification.

A Worked Example: Functional Safety

Failures can occur in sensor interfaces, compute chiplets, die-to-die links, memory, safety controllers, or actuator paths. Because they reach physical behavior, faults must be detected, isolated, and recovered within bounded safety response times.

Functional safety therefore, goes beyond the individual chiplet. The platform must provide fault detection and containment, deterministic safety signaling, coordinated safe-state control, degraded-mode operation, and evidence that the sensor-to-action path stays within its safety goals. That single architecture requirement decomposes into six specification mechanisms: platform safety control and recovery coordination; traffic classes and QoS semantics; telemetry, debug, and trace control; safety-critical data protection; reliability, degradation, and link-health reporting; and verification, compliance, and safety-case evidence.

Three of those six are shared mechanisms that also serve other constraints. That overlap is the argument for doing this work once, in a common baseline, rather than repeatedly across vendor stacks.

Figure 4. Functional safety example

Scope, and Just as Importantly, What Is Out of Scope

Ensuring the new working group stays focused, boundaries are created for what is defined as in and out of scope. For example:

In Scope

Externally visible chiplet behavior required by real-time, safety-critical physical AI
Classification of candidate requirements into baseline, optional profile, or guidance
Overlap resolution with baseline OCP FCSA and UCIe
Compliance profiles and the evidence needed to support safety claims

Out of Scope

Chiplet microarchitecture and implementation choices
Die-to-die physical and link layers already owned by UCIe and BOW
AI model, algorithm, and training behavior
Product certification and vendor-specific software stacks

The exclusions do most of the work here. By ceding the physical and link layers to UCIe and BOW, staying out of microarchitecture, and declining to touch models or certification, the group reserves one territory for itself: the observable contract between chiplets, and the evidence that the contract holds. Everything a supplier competes with remains a supplier decision.

Why Cadence Is Leading this with Co-Chair imec

The two organizations bring complementary solution expertise to the table.

Cadence contributes the system and design perspective: chiplet architecture, interface implementation, system analysis, and verification. That matters disproportionately here, because a significant share of the candidate requirements are not about moving data at all. They are about proving things. Verification, compliance, and safety-case evidence is itself a candidate requirement, calling for capability declarations, compliance-profile declarations, test results, counters, logs, timestamped event records, trace snapshots, fault-injection results, timing measurements, and security-attestation records. A specification that defines behavior but not how to evidence it delivers interoperability on paper only.

Imec contributes cutting-edge research and expertise in autonomous-edge systems, workload partitioning, chiplet architectures, and advanced integration technologies, helping identify and validate critical requirements before they become formal specifications. This contribution is already reflected in the industry working record and the Autonomous Edge Chiplet Program (AECP), where imec has helped bring together leading ecosystem players to shape the future of chiplet-based autonomous-edge platforms. Through active technical leadership, imec has driven discussions from high-level concepts toward concrete, implementable requirements. Key contributions include defining the scope of system-level interfaces, sideband communication, reset and boot mechanisms, and championing capability discovery as a foundation for interoperability. Imec has also advocated a system-centric management approach, ensuring that power and operational states are managed coherently across the entire chiplet system rather than at the individual die level.

Finally, the leadership posture suits OCP. Neither company is arriving with a finished specification to ratify. What is on the table is a baseline choice, a structure proposal, and a candidate requirement list explicitly described as an input for discussion rather than a finalized requirement set.

What’s Next

The next step is to turn this proposed framework into a community-developed specification. Cadence and imec will work through the OCP FCSA community to refine the architecture requirements, identify where existing standards can be reused, define interoperable profiles and supporting evidence, and validate the approach against representative physical AI platforms. Broad participation from chiplet suppliers, system developers, integrators, and safety and security experts will be essential to ensure the resulting standard is practical, testable, and ready to support trusted physical AI systems at scale.

Virtuoso AI Studio: Finding Specific Y-Values with Vertical Markers

Udit Rajput — Fri, 16 Oct 2026 11:00:00 GMT

Tired of manually searching waveforms for specific signal values? Read this blog to learn how vertical markers help you quickly locate every occurrence of a specific y-value across analog traces or bus signals, eliminating manual searches. With support for selective searches and keyboard shortcuts, you can analyze waveforms faster and more efficiently.(read more)

Agentic AI for PCB and Advanced Packaging Design

Reela Samuel — Thu, 15 Oct 2026 15:00:00 GMT

As AI workloads grow, more engineering challenges extend beyond the chip itself to the package that brings compute, memory, power, and cooling together. The HBM4 standard is designed to increase memory bandwidth, while evolving stacking requirements...(read more)

ケイデンス、CAE分野の大規模ユーザーカンファレンスを開催

Cadence Japan — Thu, 15 Oct 2026 00:17:53 GMT

Physical AI時代の製品開発を支える最新のシミュレーション技術、CAE活用事例、デジタルエンジニアリング戦略を紹介ケイデンス（本社：米国カリフォルニア州サンノゼ市、Nasdaq：CDNS）は、2026年11月5日（木）に、CAE分野の大規模ユーザーカンファレンス「CadenceCONNECT: Simulation Conference Japan 2026」を東京虎ノ門および大阪サテライト会場にて開催することを発表しました。本イベントでは、自動車、航空宇宙・防衛、電子機器...(read more)

CadenceCONNECT: Simulation Conference Japan 2026

Corporate — Wed, 14 Oct 2026 15:00:00 GMT

Explore the Latest Simulation Technologies, Real-World Applications, and Digital Engineering Strategies for the Physical AI Era As products become more sophisticated and complex, engineering teams face growing pressure to accelerate development, imp...(read more)

How Cadence Cares Champions Are Strengthening Communities Around the World

Yesenia Carrillo — Wed, 14 Oct 2026 15:00:00 GMT

Earlier this year, the Cadence Giving Foundation (CGF) launched the Cadence Cares Champion program across eight global sites to empower employees to take an active role in creating positive change in their communities.

At the heart of the program is a local approach to giving back. Each Champion team brings a unique understanding of the needs, opportunities, and organizations within their community. By connecting Champions with local nonprofits and providing resources to turn ideas into action, the program helps employees identify meaningful ways to get involved and make a difference in their local community.

Since the program's launch, Champions have transformed employee interests into hands-on service projects, playing a critical role in creating strong employee engagement opportunities throughout the year. Here are some of the ways our Champions are making an impact.

Highlights from Austin

The Austin Champions launched their initiatives during Earth Month in partnership with the Boys & Girls Clubs of Austin. Volunteers assembled climate learning materials that introduced children to environmental topics and encouraged them to explore how they can help care for the planet. This event united volunteers around a cause that aims to inspire the next generation to learn about sustainability and climate awareness.

Highlights from Belo Horizonte

The Belo Horizonte Champions supported a variety of causes, providing educational resources and enriching experiences for youth in the region. Most recently, champions participated in a volunteer opportunity to repair and refurbish used laptops for donation to nonprofit organizations in the local community. At the end of this ongoing project, 40 laptops will be refurbished and donated to nonprofits that have worked with the Cadence Belo site in the past—continuing to strengthen a trusted community relationship.

Volunteers also assembled AIY plush toys for children supported by Fundação Espírita Irmão Glacus (FEIG), another longtime nonprofit partner at the Belo site.

Highlights from Burlington

Burlington Champions partnered with Friends of the Middlesex Fells Reservation during Earth Month to bring employees together in support of local environmental conservation efforts and to create an opportunity for team connection outside of work. Volunteers helped remove invasive plants from restored meadows in the local area.

Highlights from Ireland

Across Cork and Dublin, Champions have embraced a wide range of causes and community partnerships. In Cork, employees assembled 2-in-1 solar lamps and power banks for families in need, in partnership with Feed Dublin, for Earth Month. The site also partnered with the Irish Bee Conservation to help refurbish a community garden and support habitats for Ireland's native bee species. In Dublin, volunteers with Ronald McDonald House Charity assembled over 80 "Grab & Go" bags containing essentials to support families with children in long-term-stay hospitals.

Highlights from Munich

In Munich, volunteers partnered with local organizations supporting individuals experiencing homelessness and other vulnerable populations. The site also deepened a long-standing partnership with Caritas Kinderof, a local nonprofit, by supporting a Summer Community Event for local families and children.

Highlights from San Jose

Earlier this summer, the San Jose Champions partnered with Women@Cadence to assemble Career Success kits designed to support women entering or re-entering the workforce. 32 employees came together around a shared mission of helping others build confidence and prepare for new professional opportunities. The council has maintained that momentum by volunteering with Second Harvest of Silicon Valley. Volunteers sorted and boxed 26,672 pounds of fruit.

Learn More

Find out more about the Cadence Giving Foundation and how contributing to our communities is part of life at Cadence.

Virtuoso AI Studio IC26.1 Now Available

Virtuoso Release Team — Wed, 14 Oct 2026 08:00:00 GMT

Virtuoso AI Studio IC26.1 production release is now available for download.(read more)

Building AI Infrastructure for Greater Choice and Flexibility

MBhatnagar — Wed, 14 Oct 2026 06:00:00 GMT

AI infrastructure is changing fast. Training and inference are putting different demands on compute, memory, connectivity, and networking, and there is no single architecture that fits every workload.

For system architects, this opens up an important question: How much flexibility can be built into the system from the start?

The answer increasingly involves giving designers more choices across memory, compute, connectivity, and packaging, while making sure those technologies work together.

Different Workloads, Different Requirements

AI training and inference may run on much of the same underlying infrastructure, but they don't behave the same way.

Training places heavy demands on memory and communication between accelerators. Inference has a different mix of requirements, including memory capacity, latency, throughput, and efficiency.

Those differences matter when choosing an architecture. A memory technology that's right for one workload may not be right for another. The same applies to interconnects and networking.

This is why AI infrastructure is becoming more heterogeneous. Architects are combining different technologies based on what they need the system to do, rather than trying to force every workload into the same design.

Figure 1: Heterogeneous applications demand distinct solutions for optimized implementations

More Choice Through Open Standards

Open standards give designers more options for how they put those systems together.

UCIe is one example. The standard provides a common approach to die-to-die connectivity and is aimed at supporting an open chiplet ecosystem. It gives the industry a standardized way to connect dies within a package rather than tying the architecture to a single implementation.

System architects are also working across a wider range of process technologies, packaging approaches, and functions. A chiplet-based approach provides another way to partition those functions, allowing compute, I/O, memory interfaces, and other functions to be integrated within the same package.

UCIe provides a standardized die-to-die connection for that environment. This gives designers a common interface as they evaluate how different functions should be partitioned and integrated.

For designers, the value is choice. Different functions can be brought together in a package while using a common interface between them.

That freedom becomes particularly useful when architects are balancing performance, power, cost, packaging, and process technology.

Interoperability Matters

Open standards provide a common foundation for bringing technologies from different suppliers and foundries into the same system. Interoperability helps designers understand how those different implementations will work together.

Verification plays an important role here, particularly as systems incorporate more functions, interfaces, and technologies.

The Same Thinking Applies Across the AI Factory

The need for choice doesn't stop at the package.

An AI system can include several kinds of connectivity, each serving a different role. PCIe, CXL, UCIe, UALink, and Ethernet-based technologies address different parts of the architecture. Memory brings another set of decisions.

Figure 2: Different connectivity, different scope, same goal: economical, rapid data transfer

The requirements also change depending on where data is moving. HBM4E and LPDDR6 address different memory needs, while PCIe supports high-speed host and device connectivity. UALink addresses accelerator-to-accelerator communication, 224G high-speed SerDes provides the underlying high-speed signaling needed for demanding connectivity applications, and UCIe connects dies within packages.

Designers need to consider what they are connecting, how much data needs to move, and the requirements of the workload. Looking at those decisions together provides a more complete view of the system than treating each interface independently.

That perspective changes the design conversation. Rather than optimizing individual pieces independently, architects can look at how memory, compute, and connectivity fit together across the system.

Designing with Room to Evolve

AI infrastructure will continue to change as workloads, memory technologies, accelerators, and interconnects advance. Building flexibility into the architecture gives designers more options as those requirements change.

Open interfaces and interoperability are an important part of that flexibility, allowing designers to choose technologies based on the needs of the system rather than a single approach.

For a deeper look at the memory, compute, and connectivity technologies shaping these systems, read our "Building AI Factories with IP Solutions" white paper.

Cadence Employees Partner with Projeto Arrastão in Brazil

Yesenia Carrillo — Tue, 13 Oct 2026 15:00:00 GMT

The Cadence Giving Foundation is proud to continue its decade-long partnership with Team4Tech, helping expand access to quality education in under-resourced communities around the world. Through this partnership, Cadence employees apply their professional skills to support education-focused nonprofits, helping them strengthen operations, improve processes, and use technology more effectively to serve learners and educators.

This year, 10 Cadence volunteers, selected from a pool of more than 90 applicants, joined a 10-week pro bono consulting project with Projeto Arrastão, a nonprofit organization in São Paulo, Brazil. Projeto Arrastão provides daily educational programming for more than 1,000 children and youth, and supports families through initiatives focused on food security, health, and well-being.

Building on previous work with Team4Tech and Projeto Arrastão, this project highlights the value of collaboration and the momentum it can create over time. As relationships deepen, each project has the opportunity to build on prior work, strengthen organizational capacity, and contribute to lasting impact for the communities Projeto Arrastão serves. Watch a recap of the 2024 project.

Beginning in August, volunteers from multiple Cadence sites and teams have been working together alongside Projeto Arrastão leaders to explore how technology can be leveraged to strengthen programs and expand impact. Through a collaborative consulting approach, the team has been sharing expertise, developing recommendations, and creating practical resources designed to deliver long-term value for the organization and the communities it serves. The project is organized around two strategic workstreams, each focused on helping Projeto Arrastão expand opportunities for learners and strengthen engagement with the broader community.

What Our Teams Are Working On

Robotics Learning Pathway and Education Team

The Robotics Learning Pathway and Education Team is working with Projeto Arrastão to develop a scalable robotics curriculum and learning pathways for students ages 15-18. The team's goal is to create learning experiences that are easy to replicate, maximizing the number of students who can benefit from technology-focused education. Their work includes designing reusable resources, challenge-based activities, and recommendations that can support both students and educators as they build STEM skills.

Digital Community Engagement Team

The Digital Community Engagement Team is focused on helping Projeto Arrastão strengthen how it connects with students, families, donors, volunteers, and community stakeholders. Working closely with non-profit leaders, the team is developing recommendations for a digital communications solution that integrates with existing processes and platforms while supporting the organization's long-term engagement goals.

Looking Forward

This work will culminate later this fall when Cadence volunteers travel to São Paulo to collaborate in person with Projeto Arrastão staff and help bring their recommendations to life.

We're excited to follow the team's journey and look forward to sharing more about the project's outcomes! Visit the Cadence Giving Foundation website for more information about programs and offerings.

When AI Becomes Part of Your Analog Design Workflow

Corporate — Tue, 13 Oct 2026 15:00:00 GMT

If you design analog or mixed-signal circuits, each silicon generation asks you to do more. Advanced nodes mean tighter margins, new device behaviors, stricter design rules, and deeper interaction between the circuit, layout, simulation, and verification tasks. Meanwhile, schedules keep shrinking. The time problem is exacerbated by the engineering effort required to set up the EDA tools themselves: creating testbenches, writing scripts, setting up simulations, analyzing results, debugging failures, and repeating the process as requirements change.

This is where agentic AI can help: by reducing the EDA burden so engineers can focus more of their time on IC design, engineering judgment, and design robustness.

Cadence Virtuoso AI Studio, when paired with the Cadence ViraStack AI Super Agent, brings agentic AI directly into the analog and mixed-signal design environment. Instead of treating AI as a separate assistant, Virtuoso AI Studio places it alongside the tools and design context engineers already use, enabling AI to move from providing general answers or optimizing individual tasks to executing and coordinating parts of the design workflow.

Turning Design Intent into Action

Testbench creation illustrates the difference.

A designer may know exactly what needs to be characterized, but translating that requirement into stimuli, measurements, analyses, operating conditions, and simulation configurations can take considerable effort. The same applies when an analysis must be repeated across multiple conditions or modified as the design evolves.

In Virtuoso AI Studio, you can use natural-language interaction to initiate these activities within the design environment, then inspect and refine the resulting setup rather than building every element manually.

See the ViraStack AI Super Agent create a Virtuoso testbench from a natural-language request:

The same approach applies to scripting. You can describe the intended task and have the ViraStack AI Super Agent generate and refine Cadence SKILL code for the Virtuoso environment. Specific Virtuoso API information and design context help make the generated code relevant to the actual task rather than simply plausible, providing a 95% productivity improvement over manual efforts.

Migration Is Where Agentic Workflows Become Powerful

Technology migration is a particularly good example of why workflow-level automation matters.

Moving an analog design to a new process isn't simple device substitution. Device characteristics such as power, sizing, and operating points may need adjustment—constraints can change, and layout requirements can introduce additional dependencies. A migrated circuit that looks structurally correct may still require substantial optimization before it meets updated specifications.

The traditional workflow involves repeated topology mapping, device and constraint translation, parameter adjustment, simulation, analysis, and correction.

The ViraStack AI Super Agent's design migration agent is designed to assist with this sequence, including topology mapping, device scaling, and optimization across technologies.

Cadence has demonstrated the approach in a 6GHz analog/RF PHY migration flow, achieving 60% faster design closure. The value lies in connecting the steps that traditionally require engineers to move between tools, analyses, and iterations manually.

Advanced Engines for Physical Implementation and Optimization

Agentic workflows extend beyond schematic-level tasks into physical implementation and optimization. With ViraStack AI Super Agent, specialized agents coordinate layout, physical verification, extraction, and post-layout optimization using the underlying EDA engines. Multimodal input allows a floorplan to be generated from an image, helping bridge the communication gap between design and layout engineers. The agent proposes placement for review and generates the floorplan only after the engineer approves it.

The underlying layout engine identifies circuit structures in the schematic and generates constraints to guide layout generation. It produces multiple prototypes that include both placement and routing, giving engineers alternatives to inspect and compare. ViraStack AI Super Agent analyzes the candidates and highlights tradeoffs such as the smallest area, fewest opens, and a balanced result, helping engineers choose the appropriate starting point.

Physical verification follows the same engineer-guided approach. Agents can check the full layout for design-rule violations, report the findings, and recommend corrections, while engineers decide which violations to address. For post-layout optimization, the agent checks the DSPF setup, identifies failing specifications, and invokes optimization that accounts for parasitic changes without requiring layout regeneration. Engineers can then request further analysis or debugging of the results, reducing manual coordination across the physical implementation flow while retaining control of design decisions.

Domain Context Matters

An AI system for analog design needs more than a natural-language interface. It needs to understand the design, the tools it operates, and the methodology behind the task. Analog and RF circuits contain relationships between topology, devices, constraints, operating conditions, measurements, and methodology that cannot be captured by simply translating a sentence into an EDA command.

The ViraStack AI Super Agent is built around that context. Its built-in skills and Virtuoso-specific knowledge give agents access to design information and Virtuoso APIs, while the mental model captures design intent, circuit functionality, and methodology knowledge in a structured format. This helps prevent AI hallucinations, improves the accuracy and speed of agent execution, and reduces token usage.

The IP Catalog extends this foundation by supporting the reuse of proven designs and providing a built-in library of hundreds of analog building blocks. Together, these capabilities give agents structured design knowledge that can be applied across workflows, helping make design automation more accurate and efficient.

Agents on Top of Proven EDA Engines

Virtuoso AI Studio continues to rely on technologies such as Cadence's Circuit Simulation and Pegasus Verification Platform, along with the broader portfolio of silicon-proven, foundry-qualified technologies that support design, layout, and optimization.

The AI layer operates on top of that foundation. Agents can determine what action is needed, invoke the appropriate capability, analyze results, and coordinate what happens next. AI may identify a potential issue or suggest a change, but circuit behavior must still be established through simulation and verification.

Agents orchestrate proven EDA engines to analyze and verify. Engineers make the final decisions.

Scaling Expertise Across the Organization

Analog design knowledge is difficult to codify. It lives in design libraries, scripts, methodologies, and in the experience of senior engineers.

Experienced designers can use AI as a force multiplier, delegating repetitive setup, analysis, scripting, and workflow coordination while focusing on architecture, topology, and difficult tradeoffs. Enterprise AI Needs Enterprise Controls

Custom design environments contain proprietary circuit structures, libraries, process information, methodologies, and IP. Any AI capability used in production must, therefore, fit within an organization's security and deployment requirements.

Virtuoso AI Studio is built on the Cadence JedAI Solution and supports secure infrastructure, including cloud-enabled and on-premises deployment models. The ViraStack AI Super Agent can also work with customer-specific design knowledge and proprietary libraries within the customer's controlled environment.

What Changes for the Analog Designer?

Engineers will continue to define what a circuit must achieve, make architectural and topology decisions, evaluate tradeoffs, interpret results, and approve changes. Agents can increasingly take on the work surrounding those decisions, from setting up analyses and generating testbenches and scripts to running defined workflows, analyzing results, supporting migration, and coordinating related tasks.

For that approach to work in custom design, AI needs more than intelligence. It needs domain expertise, established design methodologies, and proven EDA engines grounded in decades of real-world silicon design. Virtuoso AI Studio brings these capabilities together in the familiar Virtuoso environment, with the ViraStack AI Super Agent providing the agentic intelligence and Cadence EDA engines providing the engineering foundation. For analog designers, the opportunity is clear: less time spent managing the mechanics of the design flow means more time for the engineering decisions that matter.

Explore Cadence Virtuoso AI Studio and see how the ViraStack AI Super Agent can support the custom design workflow.

How AI Factories Are Redefining Data Centers and How Cadence Is Helping

Veena Parthan — Tue, 13 Oct 2026 06:31:00 GMT

Data centers are becoming AI factories—production lines for intelligence — where power, cooling, shell, and compute must be designed and operated as a single system to achieve sustainability, performance, and profitability ...(read more)

Demystifying NOP Debug Flits in PCIe Flit Mode

sabnams — Mon, 12 Oct 2026 22:35:00 GMT

Introduction

As PCIe bandwidth continues to double with every generation, complexity increases. The transition to flit mode, combined with advanced mechanisms such as replay buffers, flow control tracking, PAM4 signaling, and Forward Error Correction (FEC), has significantly improved link efficiency, but it has also made failure cause analysis far more challenging.

When performance drops unexpectedly, retry counts increase, or a switch experiences traffic congestion, debug becomes difficult, making users trace the root cause. Traditional techniques provide only a partial view of what is happening inside the link, making debug a time-consuming and often frustrating process.

To address this visibility gap, PCIe introduced the NOP.Debug flit, a standardized mechanism for transporting diagnostic information directly over the PCIe link. Instead of relying solely on external debug aids, devices can communicate valuable runtime information such as flow-control status, retry counters, buffer occupancy, trace capture triggers, and other diagnostic data through structured debug chunks embedded within a NOP.Debug flit.

Debug flits act as a built-in telemetry channel for PCIe links, rather than guessing why throughput is low or why replay activity is increasing; users can access real-time protocol state information directly from the communicating devices. The result is faster root-cause identification, improved performance analysis, and more efficient validation of complex PCIe systems.

NOP Debug Flit Layout and Details of Fields

A single debug flit can contain multiple chunks, and chunks from different vendors may coexist within the same flit. Unused space is filled using empty debug chunks.

Figure 1: NOP.Debug flit debug chunk

Figure 2: NOP.Debug flit debug chunk fields

Opcode	Debug chunk type	Purpose
0000000b	Empty debug chunk	Padding/alignment, contains no debug data
0000001b	Start capture trigger debug chunk	Trigger trace capture start
0000010b	Stop capture trigger debug chunk	Trigger trace capture stop
0000011b	FC information tracked by transmitter	TX flow-control debug
0000100b	FC information tracked by receiver	RX flow-control debug
0000101b	Flit mode transmitter retry flags and counters	TX retry status and counters
0000110b	Flit mode receiver retry flags and counters	RX retry status and counters
0000111b	Buffer occupancy debug chunk	Reports current buffer occupancy
0001000b	Link debug request debug chunk	Requests debug information from link partner

Table 1: PCI-SIG-defined debug chunk Opcodes

Advantages of Debug Flits

Instead of relying entirely on internal DUT signals, verification environments can now observe protocol state through architecturally defined mechanisms.

This improves:

Root-cause analysis
Debug productivity
Functional coverage
Silicon correlation
Interoperability testing

Debug Flits Verification

From a verification standpoint, debug flits introduce an entirely new feature set that must be validated.
The challenge is not simply verifying that a debug flit is transmitted, but one must ensure that the debug information contained within the flit accurately reflects the internal state of the DUT.
This shifts verification from validating protocol transactions to validating protocol introspection.

For this, some crucial negative scenarios must include:

1. Stress Testing with High-Volume Traffic and Credit Starvation

This scenario verifies how the DUT behaves when flow-control credits are exhausted under heavy traffic conditions. Debug flits carrying flow control information help determine whether throughput degradation is caused by credit starvation, incorrect credit accounting, or transmission throttling.

2. Flit Replays Caused by CRC/FEC Error Injection

Creating error injection scenarios by CRC or FEC corruption, such that replay mechanism is triggered and validate retry behavior. Additionally, debug flits provide visibility into retry counters and replay activity, helping confirm that replay handling and sequence-number management are functioning correctly.

3. Handling Corrupted Debug Flit Headers

A robust PCle implementation must safely detect and discard malformed debug flits without affecting normal traffic. Verification should ensure that corrupted opcodes, invalid lengths, or malformed headers are handled gracefully and do not cause protocol errors or unexpected behavior.

4. Buffer Occupancy Reporting

Buffer occupancy debug chunks provide insight into congestion within endpoints or switches. By creating traffic hotspots and buffer pressure scenarios, validation of the reported occupancy can be done to check whether it accurately reflects the actual buffer usage and helps identify performance bottlenecks quickly.

Conclusion

As PCIe systems continue to grow in bandwidth, scale, and complexity, the ability to understand what is happening inside the link becomes increasingly important. Debug flits represent a major step forward in PCIe observability. By providing standardized access to flow-control state, retry information, buffer occupancy, and trace-capture controls, they enable engineers to debug complex protocol issues with significantly greater efficiency.

In the flit era of PCIe, debug flits are not just another protocol feature. They are a powerful visibility framework that transforms debugging from guesswork into insight. Cadence PCIe VIP solutions are proven to verify the PCIe7 features and provide a seamless usage model to cater to the verification of these complex features.

More Information

For more info on how Cadence PCIe Verification IP and TripleCheck enable users to confidently verify these new disruptive changes, see our VIP for PCI Express, VIP for Compute Express Link, and TripleCheck for PCI Express.
For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website. 
If you have feedback or need more information, reach out to us at talk_to_vip_expert@cadence.com.

Sigrity and Systems Analysis 2026.1 Release Now Available

SigrityReleaseTeam — Mon, 12 Oct 2026 22:15:00 GMT

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2026.1 release is now available for download at Cadence Downloads. This blog provides quick access to software downloads, documentation, and release resources, and highlights some of the key capabilities and enhancements available in this release.(read more)

Why Protocol Compliance Is Not Enough: Performance Verification with ATP

PratikKumarGupta — Mon, 12 Oct 2026 22:00:00 GMT

Constrained-random stimulus proves that an interconnect is functionally correct. It cannot prove that the interconnect will sustain the bandwidth of real traffic demands. Adaptive Traffic Profiles were defined to answer that second question, and Cadence Verification IP implements the model in full.

A fully passing Advanced eXtensible Interface (AXI) test suite and a system that misses its performance targets in the lab are not a contradiction. The conventional stimulus is written to exercise protocol corners, so it issues bursts as fast as the subordinate will accept. Real traffic sources behave nothing like that. A camera pipeline or a display controller produces a steady, rate-limited stream of bytes and stalls when its buffer runs out of space. A stimulus that ignores that behavior measures peak throughput on an idle fabric, which is rarely the number that decides whether a design ships.

What Adaptive Traffic Profiles Describe

Adaptive Traffic Profiles, defined by Arm as part of the AMBA specification family, take a different approach from a conventional sequence. Rather than describing individual transactions, a profile describes a traffic source or sink that sits behind a first-in, first-out (FIFO) buffer. Three parameters carry most of the meaning: the rate in bytes per clock cycle at which the buffer drains or fills, the buffer depth, and whether the buffer starts empty or full.

Traffic then generates itself from that description. A read profile models a consumer: the buffer drains at the specified rate, and a transaction is issued only when enough space exists to hold the data that will be returned. A write profile models a producer: the buffer fills at the specified rate, and a transaction is issued only once enough data has accumulated to send.

The rate always applies to the traffic side of the buffer; the bus drives the other side. That asymmetry is the whole model.

The word adaptive is the important one. Because the buffer level responds to the latency the design under test actually returns, a profile throttles itself when the fabric gets congested and catches up when the fabric clears. Traffic shapes itself around the design rather than being replayed blindly at it.

Two loops run concurrently. The buffer fills and drains every cycle, while the issue loop consults the level before sending anything, which is where self-throttling comes from.

That property is also what makes a profile portable. Because it expresses a requirement rather than a fixed transaction list, the same description of a video pipeline holds its meaning in a block-level simulation, a full system run, an emulation platform, and a fabric that has since been reconfigured.

What the Model Demands of an Implementation

Expressing traffic this way is straightforward on paper and demanding in practice. A faithful implementation has to track buffer occupancy against in-flight data every cycle, convert a bandwidth figure into issue decisions, generate the address and identifier patterns the specification defines, honor outstanding-transaction limits, reproduce channel-level handshake timing, and do all of it without ever emitting a transaction that breaks protocol rules.

How Cadence Verification IP Delivers the Model

The Cadence Adaptive Traffic Profiles solution is built on the AMBA Verification IP, so profiles run inside a standard Universal Verification Methodology (UVM) environment and compose with existing stimulus rather than replacing it.

Coverage across the AMBA family

Profiles drive AXI, the Advanced High-performance Bus (AHB), AXI Coherency Extensions (ACE) with control over the non-shareable, inner, outer, and system coherency domains, and the Coherent Hub Interface (CHI). Protocol-independent behavior is shared, so a profile written for one protocol carries the same meaning on another. Both Manager-side and Subordinate-side traffic can be modeled.

The full pattern vocabulary

Addresses follow sequential, random, static, wrapping, or two-dimensional patterns, the last describing image-style access through an X range, a Y range, and a stride. Identifiers can be random, fixed, cycling, unique, or drawn from a supplied list, and generated addresses can be constrained to an alignment boundary.

Timing fidelity beyond the rate

Bandwidth is specified as a real number rather than a coarse approximation, outstanding transactions are capped independently, profile start can be offset, and the delay between consecutive transactions can be fixed or normally distributed around a mean. The specification's channel-level handshake delay parameters are supported under their standard names, so a timing requirement transfers directly from an architecture document into the testbench.

Protocol legality guaranteed

Bursts generated from a bandwidth figure are automatically split at the AXI 4KB boundary and the AHB 1KB boundary, and unaligned transfers are handled. A performance requirement cannot accidentally become a protocol violation.

Measurement built in

Every profile tracks the minimum and maximum levels its buffer reached, reports them per burst and per profile, and raises a warning whenever the buffer touches empty or full. The performance result is an output of the run, not something that has to be reconstructed afterward from a waveform.

Repeatable, trace-driven traffic

Addresses, identifiers, and data content can be supplied from plain text files in decimal or hexadecimal, so an address trace captured from software or a previous run can be replayed exactly. Files are shared across profiles and cycle automatically when shorter than the profile requires.
Because profiles are ordinary UVM sequences, many can run concurrently and compete for the same fabric. That is where results get interesting: a profile that comfortably meets its rate in isolation and starves once its neighbors become active is precisely the finding worth having before tapeout.

Seeing the Result

A read profile requesting three bytes per cycle. The buffer holds near 900 bytes while read latency is 30 cycles, drains once latency rises to 420, and then starves for 351 cycles, continuing for 252 cycles after the congestion itself has cleared. A buffer that reaches empty once the profile is running is the failure signature.

The reported buffer levels answer the original question. A read profile whose minimum level stays well clear of zero was served comfortably throughout. One that reaches empty indicates a design that could not meet its own requirement, and the margin between that minimum and the buffer depth quantifies the headroom left for the next derivative. A bandwidth number stops being a spreadsheet entry and becomes a simulation result with a pass or fail attached.

Learn More

Performance questions are easier to answer early, while the fabric can still change. Full details of Adaptive Traffic Profiles support, including the complete parameter set and supported protocols, are available through the Cadence AMBA Verification IP documentation.

Practical High-Frequency Acoustic Simulation with the Actran Radiosity Solver

MC202605188636 — Mon, 12 Oct 2026 05:57:00 GMT

Predicting noise at high frequencies is a persistent challenge across automotive, aerospace, architectural, and industrial design because the traditional Finite Element Method (FEM) and the Boundary Element Method (BEM) can become computationally exp...(read more)

Cadence Wins Five 2026 TSMC OIP Partner of the Year Awards

Corporate — Fri, 09 Oct 2026 16:00:00 GMT

Five awards. Five areas of collaboration. One shared focus: helping customers push the limits of what is possible in semiconductor design. Cadence has been named the 2026 TSMC Open Innovation Platform® (OIP) Partner of the Year, receiving five aw...(read more)

Streamlining SI/PI Analysis with Clarity 3D Solver’s New ACE Technology

MSATeam — Fri, 09 Oct 2026 04:58:00 GMT

Today’s complex electronic designs, particularly in the context of high-speed interconnects, 3D-ICs, and advanced packaging, require robust electromagnetic (EM) simulation tools that balance accuracy, speed, and integration. Two new resources are available that introduce the new automated channel extraction (ACE) feature within the Clarity 3D Solver and highlight how the core technical advancements in this innovation address the challenges of large-scale simulation, workflow automation, and seamless integration with leading EDA platforms.

The on-demand Cadence webinar, Transform Your S/PI Analysis with Clarity 3D Solver, demonstrates the capabilities of the ACE technology, while a new product overview, Streamlining SI/PI Analysis with Clarity ACE Technology, available online and as a downloadable PDF, provides technical details of the key features.

ACE Automated Workflow

Clarity ACE technology addresses a critical industry need: the automation of partitioning and channel extraction in large EM designs. Clarity ACE technology represents a significant advancement in EM simulation automation; by automating the partitioning and extraction of complex design channels, the ACE tool streamlines what were previously manual, error-prone processes. With ACE technology, engineers can assign multiple net groups, perform simultaneous cutouts, and serialize or parallelize the entire workflow. This enables rapid reuse and adaptation of simulation setups across multiple design iterations and layouts, greatly reducing setup and post-processing times.

Traditionally, engineers manually select the nets, define partitions, and manage cutouts as individual projects. They then post-process for frequency domain comparisons or masking—a process prone to errors and inefficiency. ACE technology allows users to import layouts, assign net groups, perform cutouts, and serialize or parallelize simulations with minimal manual input. The flow has been compressed significantly, enabling designers to assign multiple net groups and do multiple cutouts all at the same time and serialize or parallelize the entire process. The figure below shows how Clarity ACE provides a single step process rather than manually manipulating different net groups.

In addition, all the data can be reused from design to design. A very quick partitioning of the entire design can be performed and all the different partitions can be visualized before the simulation is run. The solve progress and the results can be viewed through a single interface using Clarity 3D Solver’s benefits and gold-standard accuracy.

Manual sub-modeling is no longer needed, as the software intelligently segments and solves many channels of a larger system. The tool provides re-aggregation by automatically stitching results back together, providing a holistic view of system performance without the manual overhead. Pre- and post-processing is streamlined by automating the signal integrity/power integrity (SI/PI) data workflow around a high-performance solver, significantly reducing time to results.

Instead of just solving the different blocks serially, engineers can select how many different compute resources are available and how many solves and licenses of Clarity 3D Solver can be used at the same time. Simulation progress can be monitored and load and plot results obtained. As can be seen in the figure below, some of the simulations have already been completed as other ones are starting. This enables the designer to solve several or all of the problems simultaneously, depending on the available resources. Also, from this window, results can be loaded and plotted by going to the view results button.

Integration with Design and Analysis Platforms

A key differentiator of Clarity ACE technology is its deep integration with the broader Cadence ecosystem. The Clarity solver is accessible directly within the Virtuoso Layout Suite for IC-centric and module-centric workflows. Multiple fabrics, such as package modules and ICs, can be imported and simulated natively. In addition, through the Allegro X Design Platform engineers can run Clarity-based analysis workflows from the Allegro PCB and package design environment.

Conclusion

Clarity ACE technology is being employed across a range of high-impact applications, including high-speed packaging, module design, interposers, and advanced IC-level simulations. Its automation and integration capabilities have enabled customers to compress design cycles, reduce manual setup, and achieve rapid, repeatable results. The tool is actively used in customer projects.

Clarity 3D Solver and ACE technology represent a new paradigm in 3D EM simulation, combining automation, scalability, and integration to meet the demands of modern electronic design. By reducing manual effort, enabling parallelized workflows, and supporting comprehensive post-processing, these tools empower engineering teams to achieve faster, more accurate results and accelerate innovation.

To learn more about Clarity 3D Solver and ACE technology, visit the Clarity 3D Solver product page, view the webinar on demand here, and read the product brief here.

UPLI Credit Flow: Why It Matters for UALink and What It Takes to Verify It Right

AY20250725603 — Fri, 09 Oct 2026 00:00:00 GMT

The Problem Nobody Talks About Picture a world where 1,024 AI accelerator chips work shoulder-to-shoulder inside a single compute node - each one craving data as fast as it can process it, each one firing requests at its neighbours dozens of times ev...(read more)

How Cadence DSPs Put In-Cabin AI Audio On-Chip in SemiDrive's X10

DZ202608057522 — Thu, 08 Oct 2026 16:00:00 GMT

SemiDrive, an automotive semiconductor company building SoCs and MCUs for the software-defined vehicle, has licensed and integrated Cadence Tensilica HiFi 5s DSPs into its X10 next-generation AI cockpit SoC, where they form the audio and voice subsys...(read more)

BETA CAE Team Announces v25.1 HF6 Software Release

Cadence BETA CAE Software — Thu, 08 Oct 2026 15:00:00 GMT

About this Release We officially announce the last bug-fix release of the v25.1.x series for ANSA Advanced CAE Pre-Processor, EPILYSIS FEA Solver, META Post-Processor, and KOMVOS SDM Console, with critical bug fixes. Follows an overview of the mos...(read more)

UCIe 3.0: Faster Links Are Only Half the Story

Mannan — Thu, 08 Oct 2026 08:52:00 GMT

The chiplet ecosystem continues to push performance boundaries, and the latest UCIe 3.0 specification takes a significant step forward with the introduction of 48 GT/s and 64 GT/s data rates, alongside enhancements to support continuous transmission protocols and improved framing error detection and correction capabilities. Together, these features represent much more than a simple speed upgrade. They fundamentally expand the scope of workloads that can efficiently leverage UCIe-based connectivity.

More Than Just Higher Bandwidth

The move from previous generations to 48 GT/s and 64 GT/s significantly increases die-to-die bandwidth, enabling chiplet-based systems to transfer data at unprecedented rates. For AI training clusters, inference accelerators, memory-centric architectures, and large-scale compute fabrics, this additional throughput helps address one of today's biggest bottlenecks: data movement.

However, higher bandwidth brings new challenges. As bandwidth scales, the tolerance for implementation issues shrinks. Small protocol violations, corner case timing interactions, or recovery sequence bugs that might have gone unnoticed at lower speeds can manifest as level failures in complex chiplet deployments.

Enabling Continuous Transmission Workloads

One of the most significant enhancements in UCIe 3.0 is its support for protocols that require continuous transmission. A notable example is JESD204E, which introduces a UCIe optimized link layer for transporting high speed converter data across chiplet-based systems. By providing the high bandwidth, low latency foundation needed for sustained data streams, UCIe 3.0 extends its reach beyond traditional compute connectivity and into specialized data-intensive applications.

Historically, many interconnect protocols have relied on burst-oriented or packet-based communication models, where transmission gaps occur naturally. Emerging workloads are increasingly different. AI data pipelines, streaming accelerators, memory fabrics, and converter-centric systems often require a continuous, deterministic flow of information across chiplets.

Supporting these workloads demands more than higher bandwidth alone. The interconnect must sustain uninterrupted data transfer while maintaining framing integrity, link reliability, and protocol correctness across a wide range of operating conditions.

Reliability Becomes a First-Class Requirement

At higher speeds and under continuous traffic conditions, framing accuracy becomes increasingly critical. To strengthen link robustness, UCIe 3.0 introduces enhanced mechanisms for valid framing error detection and correction. These capabilities help identify framing-related issues before they propagate across the system, improving overall reliability and resiliency.

The Verification Challenge

While these features unlock new possibilities, they also introduce a new generation of verification challenges. Verification teams must validate not only the happy path, but also countless corner cases:

Can the design reliably sustain 48 GT/s and 64 GT/s operation?
Does continuous transmission behave correctly during congestion and flow control events?
Are framing errors detected precisely when they occur?
Are the correction and recovery mechanisms executed according to the specification?
How does the system behave when multiple protocol features interact simultaneously?
Can interoperability be maintained across different implementations?

The difficulty lies not in testing a few isolated scenarios, but in exercising the enormous state space created by high speed operation, continuous traffic patterns, link recovery flows, and error injection scenarios.

Why Advanced VIP Matters

This is where a comprehensive verification solution becomes critical. Cadence UCIe VIP provides a protocol-aware verification environment that enables engineers to validate both mainstream and advanced UCIe 3.0 features efficiently.

For higher speed operation, the Cadence UCIe VIP helps verify link training, speed negotiation, protocol compliance, and data integrity across supported data rates. For continuous transmission use cases, the VIP can generate realistic traffic patterns, exercise streaming scenarios, and validate system behavior under stress conditions.

Equally important, the Cadence UCIe VIP provides extensive error injection and protocol checking capabilities, enabling teams to verify framing error detection, correction, recovery behavior, and overall protocol robustness before silicon.

By combining automated protocol compliance checking, comprehensive coverage collection, configurable traffic generation, and interoperability-focused verification, engineers can focus on uncovering corner case issues rather than building complex verification infrastructure from scratch.

Looking Ahead

What makes UCIe 3.0 exciting is not simply the introduction of 48 GT/s and 64 GT/s operation. It is the combination of higher bandwidth, continuous transmission enablement, and enhanced reliability mechanisms that broadens the range of protocols and workloads that can leverage the UCIe ecosystem.

But as performance and protocol complexity increase, verification becomes a key enabler of successful deployment. Advanced verification solutions such as Cadence UCIe VIP play a crucial role in helping engineering teams confidently adopt these new capabilities while maintaining interoperability, compliance, and reliability.

Because in the world of chiplets, faster links are only half the story. Confident verification is the other half.

Learn more about Cadence UCIe Verification IP on the Simulation VIP for UCIE | Cadence or simply reach out to our Cadence Verification IP experts at talk_to_vip_expert@cadence.com.

Cadence Recognized Among Fast Company’s Next Big Things in Tech 2026

Corporate — Wed, 07 Oct 2026 16:30:00 GMT

Fast Company has named Cadence to its 2026 Next Big Things in Tech Awards list, particularly recognizing it as one of the 6 Next Big Things in Computing, Chips, and Foundational Technology. This recognition is an acknowledgment of the work we do eve...(read more)

How to Verify and Signoff AI-Generated Design Data

Reela Samuel — Wed, 07 Oct 2026 09:35:00 GMT

An agentic AI system can generate and iterate through design changes at a scale and speed that conventional workflows cannot. It can generate RTL, propose an ECO, modify a constraint, create a verification property, or explore an implementation opti...(read more)

Showcase Your PCB and Package Design Expertise with Digital Badges

ulrike — Tue, 06 Oct 2026 09:58:00 GMT

PCB and Package Design engineers are behind many of today's most innovative electronic products. From library development and schematic creation to advanced package design and SI/PI analysis, their expertise drives successful product development....(read more)

Cadence Community

Clipped Voronoi Meshing: Deterministic Grids for Industrial-Scale LES

When AI Moves the World: Building a Chiplet Standard for Physical AI

What Makes Physical AI Different

Perceiving and Reacting

Acting Safely

Across the Whole Platform

Why Chiplets Matter, and What They Complicate

A Physical AI Profile for OCP FCSA

From Constraints to Architecture

A Worked Example: Functional Safety

Scope, and Just as Importantly, What Is Out of Scope

In Scope

Out of Scope

Why Cadence Is Leading this with Co-Chair imec

What’s Next

Virtuoso AI Studio: Finding Specific Y-Values with Vertical Markers

Agentic AI for PCB and Advanced Packaging Design

ケイデンス、CAE分野の大規模ユーザーカンファレンス を開催

CadenceCONNECT: Simulation Conference Japan 2026

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Highlights from Austin

Highlights from Belo Horizonte

Highlights from Burlington

Highlights from Ireland

Highlights from Munich

Highlights from San Jose

Learn More

Virtuoso AI Studio IC26.1 Now Available

Building AI Infrastructure for Greater Choice and Flexibility

Different Workloads, Different Requirements

Figure 1: Heterogeneous applications demand distinct solutions for optimized implementations

More Choice Through Open Standards

Interoperability Matters

The Same Thinking Applies Across the AI Factory

Figure 2: Different connectivity, different scope, same goal: economical, rapid data transfer

Designing with Room to Evolve

Cadence Employees Partner with Projeto Arrastão in Brazil

What Our Teams Are Working On

Robotics Learning Pathway and Education Team

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Looking Forward

When AI Becomes Part of Your Analog Design Workflow

Turning Design Intent into Action

Migration Is Where Agentic Workflows Become Powerful

Advanced Engines for Physical Implementation and Optimization

Domain Context Matters

Agents on Top of Proven EDA Engines

Scaling Expertise Across the Organization

What Changes for the Analog Designer?

How AI Factories Are Redefining Data Centers and How Cadence Is Helping

Demystifying NOP Debug Flits in PCIe Flit Mode

Introduction

NOP Debug Flit Layout and Details of Fields

Advantages of Debug Flits

Debug Flits Verification

1. Stress Testing with High-Volume Traffic and Credit Starvation

2. Flit Replays Caused by CRC/FEC Error Injection

3. Handling Corrupted Debug Flit Headers

4. Buffer Occupancy Reporting

Conclusion

More Information

Sigrity and Systems Analysis 2026.1 Release Now Available

Why Protocol Compliance Is Not Enough: Performance Verification with ATP

What Adaptive Traffic Profiles Describe

What the Model Demands of an Implementation

How Cadence Verification IP Delivers the Model

Coverage across the AMBA family

The full pattern vocabulary

Timing fidelity beyond the rate

Protocol legality guaranteed

Measurement built in

Repeatable, trace-driven traffic

Seeing the Result

Learn More

Practical High-Frequency Acoustic Simulation with the Actran Radiosity Solver

Cadence Wins Five 2026 TSMC OIP Partner of the Year Awards

Streamlining SI/PI Analysis with Clarity 3D Solver’s New ACE Technology

ACE Automated Workflow

Integration with Design and Analysis Platforms

ケイデンス、CAE分野の大規模ユーザーカンファレンスを開催