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  • Atreya
    Verifying Design Changes Does Not Have to Be Difficult and Tedious — Make It Easier with Conformal Equivalence Checker
    By Atreya | 14 Apr 2021
    You put your design through a multitude of tools for various transformations. Going back to formal verification in between every change to rely on your simulation tools can be a rigorous approach, but wait... there is an easier way: Use equivalence checking, with Conformal® Equivalence Checker....
    0 Comments
    Tags:
    conformal | formal | Logic Design | Equivalence Checking | Digital Implementation | verification
  • Paul McLellan
    Benedict Evans on Tech 2021: Harder Problems and Regulation
    By Paul McLellan | 14 Apr 2021
    This is a continuation of last week's post Benedict Evans' on Tech in 2021 . That covered Covid Acceleration and the Great Unbundling. Today, the rest of his presentation. Harder Problems In the first 20 years of the inter...
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    Tags:
    benedict evans | Internet | regulation
  • Arif Khan
    First Look: Cadence Subsystem SoC for PCIe 5.0
    By Arif Khan | 13 Apr 2021
    If a picture is worth a thousand words, a video tells you the entire story. Cadence's subsystem SoC silicon for PCI Express (PCIe) 5.0 demo video shows you how we put together the latest technology in TSMC's advanced FinFET technology to bring to market a compelling, low-power solution and tested it...
    0 Comments
    Tags:
    controller IP | CXL | PCI Express 5.0 | Design IP | IP | PHY | Gen5 | PCIe | semiconductor IP | Design and Verification IP | SerDes | Compute Express Link | SerDes IP | PCI Express
  • Parula
    Virtuoso Video Diary: “Training bytes” 助推知识传播—第4部分
    By Parula | 13 Apr 2021
    我们生活在一个日趋复杂的世界中,尽可能的使用和组合各种工具及平台,以及其它的可用功能,这对于我们而言至关重要. 在此博客中, 我们将介绍如何使用Spectre Simulation 平台快速获得最优结果.
    0 Comments
    Tags:
    Chinese blog | Virtuoso | Spectre | Online Support
  • Niharika1
    BoardSurfers: Training Insights: Setting Up and Using Pin Delays in Constraint Manager
    By Niharika1 | 13 Apr 2021
    Pin delays are used to specify the time delay or length from the internal package connection to the pin’s mounting layer. It is critical to include pin delays when tuning high-speed nets to ensure signal performance. Pin delays are used in the ...
    0 Comments
    Tags:
    17.4 | cadence | BoardSurfers | Cadence Online Support | Constraint Manager | 17.4-2019 | Training Insights | Allegro PCB Editor
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