Cadence Blogs

Augment Certainty of Bio-simulation Studies with Computational Fluid Dynamics

Computational fluid dynamic (CFD) simulations have a lot to offer for a top-level…

Veena Parthan 19 Oct 2022 • 4 min read

openeye scientific , molecular sciences , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , Cadence CFD , drug delivery mechanism

カスタムIC／ミックスシグナル

Spectre Tech Tips: ダイナミック電流密度チェック

デバイスと回路の信頼性は、個々のMOSFET デバイスが短時間に消費する電力と、発生する熱の量に大きく依存しています。信頼性と寿命を向上するために、回路設計者はデザイン内のデバイスの消費電力を最適化する必要があります…

Custom IC Japan 19 Oct 2022 • 1 min read

spectre aps , Spectre 21.1 , Dynamic Checks , Dynamic design checks , Spectre Circuit Simulator , Spectre , japanese blog , spectre x

USB4 Version 2.0 – Next frontier in High-Speed Data Tunneling

USB4 Version 2.0 specification was recently released by the USB Promoter Group. This…

Neelabh 19 Oct 2022 • 2 min read

USB4 VIP , USB4v2 , usb4 , USB4 Version 2

Last Week at Fidelity CFD

It's Monday and time to look back on what happened last week here at Cadence Fidelity…

John Chawner 19 Oct 2022 • 3 min read

CFD , turbomachinery , webinars , Pointwise , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , Mesh Generation

On-Demand Webinar - Predicting Aerodynamic Flow Around Automotive Vehicles

Predicting aerodynamic flow physics around automotive vehicles is a complex endeavor…

AnneMarie CFD 19 Oct 2022 • less than a min read

CFD , Automotive , external aerodynamics , automotive engineering , featured , Computational Fluid Dynamics , fluid dynamics , simulation software , Aerodynamics

Digital Design

Voltus Voice: How to Find Functional Power Vectors that Matter Quickly

Vector profiling enables ASIC designers to quickly identify areas with maximum activity…

bertrandgenneret 19 Oct 2022 • 6 min read

switching power , Low Power , Voltus IC Power Integrity Solution , power consumption , Power Signoff , Power Profile , Digital Implementation , switching activity , Power Analysis , vector profiling

Life at Cadence

Formula 1: Hybrid Design vs. Density and Compact Design Optimization

Understand the role that density and compact design optimization play when designing…

Corporate 19 Oct 2022 • 5 min read

F1 , optimization , density , formula 1

USB-C – The Least Standard Standard Ever

In a post in our verification blog , Neelabh Singh told us that USB4 Version 2.0…

Paul McLellan 19 Oct 2022 • 3 min read

usb 4.0 , USB , USB-C

Leveraging the PCIe for CXL Mode Link Up Using Alternate Protocol Negotiation Te…

An Alternate Protocol negotiation (APN) can be understood as a non-PCIe protocol…

Somya Bansal 19 Oct 2022 • 3 min read

CXL , Verification IP , cadence , Functional Verification , VIP , PCIe , coherency , TripleCheck

System, PCB, & Package Design

HOT CHIPS: Arm's Morello

HOT CHIPS was back in the summer, and I covered it in two overview posts (and some…

Paul McLellan 18 Oct 2022 • 5 min read

morello , hot chips , ARM , cheri , capability

Enflame Unveils Lab-Correlated Design and Analysis Methodology for 2.5D HBM Desi…

At CadenceLIVE China 2022, AI-startup, Enflame Technology, revealed how their engineering…

Sigrity 17 Oct 2022 • less than a min read

SI , PI , IC , SSN anlysis , IC Packaging , Sigrity XcitePI , Co-Analysis , Power Integrity , CadenceLIVE China , Advanced-IC Package design , silicon interposer , Signal Integrity , 2.5D HBM , cadencelive , Sigrity SystemSI , Clarity 3D Solver , simulation

CXL 3.0 Scales the Future Data Center

CXL is emerging as the industry focal point for coherent I/O with Open CAPI and Gen…

Claire Ying 17 Oct 2022 • 4 min read

CXL , Verification IP , Memory , System Design and Verification , VIP , PCIe , Funcional Verification , coherency , PCIe 6.0 , AI , data centers , cloud computing , verification

CadenceLIVE Boston: State-of-the-Art Heterogeneous Integrated Packaging (SHIP)

Congress and the military love to come up with cute acronyms for programs, and so…

Paul McLellan 17 Oct 2022 • 3 min read

RF , SiP , ship , ship-rf , 3dhi

Unraveling New Introduced PCIe 6.0 L0p

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu 17 Oct 2022 • 4 min read

Verification IP , VIP , PCIe , pcie gen6 , verification

Streamline Reading and Writing Files from Fidelity Pointwise

For a CFD solution, a CAD geometry goes in and a CFD mesh comes out! Only if it was…

Veena Parthan 16 Oct 2022 • 6 min read

Meshing Monday , geometry cleanup , Computational Fluid Dynamics , engineering , simulation software , Mesh Generation , Cadence CFD , Fidelity Pointwise

Unraveling PCIe 6.0 Training Sequences Update and Verification Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu 14 Oct 2022 • 4 min read

Verification IP , PCIe , pcie gen6 , verification

System, PCB, & Package Design

System Analysis Knowledge Bytes: Simplifying Signal and Power Integrity Analysis…

This System Analysis Knowledge Bytes blog describes how Sigrity Aurora can help simplify…

deeptik 14 Oct 2022 • 8 min read

IDA , Sigrity Aurora , Sigrity Topology Explorer , Power Integrity , SI/PI Analysis , Allegro Package Designer , Signal Integrity , PCB design , Clarity 3D Solver