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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Analog/Custom Design

Virtuosity: 19 Things I Learned in April 2015 by Browsing Cadence Online Support

Application Notes 1. Spectre PSPICE Netlist Support Spectre technology enables…

• 5 min read
AMS , ADE XL , UNL , Monte Carlo , Virtuoso , Liberate , VLS XL , VCP

Whiteboard Wednesdays

Whiteboard Wednesdays—Type C Connector and USB Controllers

In this week's Whiteboard Wednesdays video, Jacek Duda explains the implications…

• less than a min read
Whiteboard Wednesdays , controller , USB , Type C connector , On-the-go

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Split Plane Association? 16.6 Has Several New…

In the 16.6 Allegro PCB Editor release, net associations to split planes are now…

• 1 min read
PCB Layout and routing , Cadence Design Systems , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—Innovations in the DRAM World

In this week's Whiteboard Wednesdays video, Lou Ternullo reviews the latest DRAM…

• less than a min read
Whiteboard Wednesdays , IP , DRAM , system level , density

Verification

Indago Protocol Debug and IP Verification

Nothing beats knowing, a late electronics-industry veteran used to say. That’s no…

• 3 min read
IP , cadence , debug , Functional Verification , electronics system design , Indago , engineering , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Why Buy Memory Models?

In this week's Whiteboard Wednesdays video, Susan Peterson breaks down why you should…

• less than a min read
Whiteboard Wednesdays , IP , memory models

System, PCB, & Package Design 

What's Good About the Allegro Design Entry HDL Front to Back Flow Cadence Training…

Hear what Bruce Imai—a Cadence Educational Services course developer—Cadence Application…

• less than a min read
PCB Layout and routing , Routing , electrical constraints , 16.6 , High Speed , hierarchical schematics , PCB Editor , Design Entry HDL , Layout , PCB design , Grzenia , Schematic , Allegro

SoC and IP

Speed, Function, and Technology as Key Factors for USB Applications

USB is regarded as the world’s most popular serial interface, with over 1 billion…

• 2 min read
Design IP , host , controller , PHY , OTG , 1.1 , USB , Dual Mode , ip cores , 2.0 , Dual Role , device , 3.0

Whiteboard Wednesdays

Whiteboard Wednesdays - Analog Front-End Interfaces Explained

In this week's Whiteboard Wednesdays video, Bob Salem takes a closer look at analog…

• less than a min read
Whiteboard Wednesdays , IP , wireless communications , analog front end , AFE

Digital Design

Five Things You Didn’t Know About High-level Synthesis

Most of you have heard about the promises of high-level synthesis (HLS). Things like…

• 4 min read
High-Level Synthesis , ECO , Conformal ECO Designer , cadence , Blu Wireless , Forte , Stratus , HLS

Whiteboard Wednesdays

Whiteboard Wednesdays – Why a New DSP Is Needed to Support Today's Sensors

In this week’s Whiteboard Wednesdays, Chris Rowen highlights the requirements of…

• less than a min read
DSP , Whiteboard Wednesdays , IP , Chris Rowen , IoT , sensors , Tensilica , Internet of Things

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Suppression of Unassigned Indirect Vias? 16…

The suppression of unassigned indirect vias is now supported in Allegro PCB Editor…

• 1 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro 16.6 , PCB Editor , Layout , via , PCB design , Grzenia , Allegro PCB Editor , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—DDR Subsystems and Latency

In this week's Whiteboard Wednesdays video, Lou Ternullo discusses DDR subsystems…

• less than a min read
Whiteboard Wednesdays , IP , DDR , latency

SoC and IP

Don’t Miss Embedded Vision Summit on May 12

One of the best, most insightful (no pun intended) conferences each year is the Embedded…

• 1 min read
DSP , Chris Rowen , IVP , vision processing , embedded vision , Tensilica , vision

SoC and IP

Next-Generation DDR4 and LPDDR4 IP in TSMC 16FF+ Enable 200Gb+ Data Transfers for…

Consumer demand for entertainment and communication is changing the architecture…

• 5 min read
DDR4 , LPDDR4 , IoT , cloud , Design IP and Verification IP , 16FF+

SoC and IP

CDNLive IP Track Presentations Available Online

With more than 100 presentations, live product demos, designer expo, and numerous…

• 2 min read
CDNLive , Tensilica , Design IP and Verification IP

SoC and IP

Interconnect Validator and its Significance

Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP…

• 2 min read
Interconnect Workbench , AMBA ACE , Interconnect Validator , VIP , AMBA CHI , SoC , OCP , Design IP and Verification IP

Whiteboard Wednesdays

Whiteboard Wednesdays—What Makes a Protocol Standard Stick

In this week's Whiteboard Wednesdays video, Susan Peterson takes a closer look at…

• less than a min read
Whiteboard Wednesdays , IP , UniPro , protocol , VIP , MIPI , DisplayPort , LLI , HMC , M-PCIe , HBM , PCIe , HDMI , PCI Express , SSIC

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Associative Dimensioning Updates? 16.6 Has Several…

With the 16.6 Allegro PCB Editor release, custom text can now be specified for any…

• 2 min read
PCB Layout and routing , Allegro 16.6 , PCB Editor , Layout , PCB design
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