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  • Paul McLellan
    Sunday Brunch Video for 11th April 2021
    By Paul McLellan | 11 Apr 2021
    https://youtu.be/D29rGqkkf80 Made in "Hawaii" (camera Ziyue Zhang) Monday: Dynamic Duo 2: The Sequel Tuesday: Gall's Law and Big Ball of Mud Wednesday: Benedict Evans on Tech in 2021 Thursday: Cadence/Samsung Automotive Reference F...
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    Tags:
    sunday brunch
  • Paul McLellan
    Have You Heard of ISO 21434? You Will
    By Paul McLellan | 9 Apr 2021
    You probably already know what ISO 26262 is. If you don't, then you can find out in several previous posts: "The Safest Train Is One that Never Leaves the Station" History of ISO 26262 ISO 26262...Chapter 11 What to Do About IP Developed Before...
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    Tags:
    automotive | iso 21434 | ISO 26262
  • SPB Japan
    Allegro System Capture のやり方で設計する
    By SPB Japan | 9 Apr 2021
    ロジック設計エンジニアのためのシリーズ 洗練された新しい設計エコシステム、Allegro® System Captureの世界へようこそ。この ASCENT シリーズでは、Allegro System Captureとは何か、 部品登録やデザイン生成などレイアウトファイル作成につながるステップにおける様々な機能やフローをこのアプリケーションの中でどのように利用できるか、を探っていきます。 何よりもまず、あなたが抱いているかもしれない疑問について... &n...
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    Tags:
    17.4 | 17.4-2019 | Allegro System Capture | japanese blog
  • Parula
    Virtuoso Video Diary: Knowledge Booster - 5G mmWave Handset System Design
    By Parula | 8 Apr 2021
    In this blog we would like to let you know – amongst other things - how to implement a transceiver RFIC module of a 5G mmWave mobile handset working at 28GHz.
    0 Comments
    Tags:
    training | Cadence training | digital badges | training bytes | Virtuoso | Cadence certified | Virtuoso Video Diary | Custom IC Design | online training | Custom IC
  • Custom IC Japan
    Virtuoso Video Diary: Virtuoso Visualization and Analysis XLのTabular Graph
    By Custom IC Japan | 8 Apr 2021
    読者の皆様、こんにちは。 今回は、Virtuoso Visualization and Analysis XLのエキサイティングな機能であるTabular Graphについてご紹介したいと思います。 IC6.1.8 ISR14/ICADVM20.1 ISR14で導入されたTabular Graph機能は、信号を表形式の列にプロットすることができます。 これまでは、選択した信号を右クリックして Send To -> Table オプションを選択すると、総合的な波形データを...
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    Tags:
    Analog Design Environment | ViVa-XL | custom/analog | ADE Explorer | Analog Simulation | ADE | Virtuoso | ViVA | Virtuosity | japanese blog | Custom IC Design | ADE Assembler
  • Paul McLellan
    Cadence/Samsung Automotive Reference Flow
    By Paul McLellan | 8 Apr 2021
    Today, Cadence and Samsung announced the availability of an Automotive Reference Flow for Samsung Foundry's 14LPU process technology. In the press release back in 2016 when the process was first announced, Samsung said: Samsung’s fourth-ge...
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    Tags:
    automotive | Genus | functional safety | Safety | Samsung | samsung foundry | Innovus | fusa | reliability
  • Paul McLellan
    Benedict Evans on Tech in 2021
    By Paul McLellan | 7 Apr 2021
    Benedict Evans used to work in Silicon Valley for Andreesen-Horowitz (a16z) but he returned to the UK (he's British). But one thing hasn't changed—he still does a big Powerpoint early in the year about the major internet trends that are driving...
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    Tags:
    benedict evans | Internet
  • Shikha Jain
    BoardSurfers: Installation Know-How: Using Third-Party Tools with Cadence OrCAD and Allegro Products
    By Shikha Jain | 6 Apr 2021
    The add-on model is applicable everywhere! You can choose a basic version of the car and add-on products make it faster, nicer, or more special. Air travel add-on includes seat reservation, food, priority check-in, and extra baggage. When you purchas...
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    Tags:
    Installation Know-How | 17.4 | cadence | install | BoardSurfers | Allegro OrCAD Installer | 17.4-2019 | Download Manager | OrCAD | Allegro
  • Paul McLellan
    Gall's Law and Big Ball of Mud
    By Paul McLellan | 6 Apr 2021
    Gall's Law says: A complex system that works is invariably found to have evolved from a simple system that worked. A complex system designed from scratch never works and cannot be patched up to make it work. You have to start over with a working...
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    Tags:
    design patterns | software development
  • Amit Sanadhya
    Virtuoso Video Diary: Incremental Simulations with Enhanced Reference Histories and New Merge Histories Feature
    By Amit Sanadhya | 5 Apr 2021
    Gone are the days of exporting results from multiple interactive runs and combining them into Excel spreadsheets for analysis. The new Reference Histories and Merge Histories flows address all these concerns. Click here to know more.
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    Tags:
    Analog Design Environment | ICADVM18.1 | Analog Design Environment | Virtuosity | Virtuoso Video Diary | Custom IC | IC6.1.8 | Assembler | ADE Assembler
  • candyyu
    RF/微波設計 隨選豐富影片信手拈來!
    By candyyu | 5 Apr 2021
    Cadence 團隊為客戶精選從去年至今年RF/微波設計一系列精采演講,內容涵蓋Cadence如何整合RF/微波設計的產品組合,提供市場上最全面的RF設計解決方案,以及進一步運用其特色增強設計並提高生產率! 本系列影片由Cadence AWR 產品部及RF 微波應用專家Milton Lien博士精彩講解,若您已錯過先前演說,那麼請把握Cadence精選視頻重播,只要註冊Cadence.com加入會員,豐富資訊即可信手捻來! 1. 使用Cadence AWR軟體為高功率RF應用設計GaN功率放.....
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    Tags:
    5G | awr | EMX | taiwanese blog
  • Paul McLellan
    Dynamic Duo 2: The Sequel
    By Paul McLellan | 5 Apr 2021
    There's a story, probably apocryphal, about a screenwriter pitching a movie in Hollywood. The potential producer says "It looks like a great movie. It's a pity nobody has made it already so we could make the sequel". Given that almost every other mov...
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    Tags:
    dynamic duo | prototyping | protium x2 | palladium z2 | Emulation | FPGA prototyping | software development | firmware development
  • Rachna2018
    ASCENT: Ready, Steady, Design ... Even With Existing Libraries
    By Rachna2018 | 1 Apr 2021
    After a quick overview of Allegro® System Capture , let’s start at the very beginning of the design process. Where are the parts? What parts can you use when creating an Allegro System Capture logical design? Parts, as you know, are the basi...
    0 Comments
    Tags:
    System Capture | 17.4 | cadence | logical design | Allegro Unified Libraries | 17.4-2019 | Front-end PCB design | logic-capture | PCB design | Allegro System Capture | ASCENT | Schematic | Allegro
  • Paul McLellan
    Offtopic: Podcasts
    By Paul McLellan | 1 Apr 2021
    Tomorrow is another Cadence global holiday. None of us will be working and Breakfast Bytes will not appear. I rather like these special Cadence holidays, compared to true public holidays, since most people are working. If you go to a park, the p...
    0 Comments
    Tags:
    offtopic | podcast
  • Custom IC Japan
    Virtuoso Meets Maxwell: EMX Planar 3D Solverで受動素子と能動素子を持つRFブロックをシミュレートするには?
    By Custom IC Japan | 1 Apr 2021
    'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
    0 Comments
    Tags:
    AXIEM | VLS EXL | EM Solver | Virtuoso Meets Maxwell | Electromagnetic analysis | black boxing | Virtuoso | EMX | ICADVM20.1 | japanese blog | Clarity 3D Solver | Virtuoso Layout Suite EXL
  • Custom IC Japan
    Start Your Engines: SimVision Mixed-Signal Debug Optionを使ってル・マンで優勝する
    By Custom IC Japan | 1 Apr 2021
    Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 Bonjou...
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    Tags:
    AMS Designer | Start Your Engines | simvision | analog/mixed-signal | Virtuoso | AMSD Flex Mode | japanese blog | mixed-signal design | debugging | mixed-signal verification
  • Paul McLellan
    The First Commercial Computer Shipped 70 Years Ago Today
    By Paul McLellan | 31 Mar 2021
    Today is the 70th anniversary of a very significant event in all our lives, even if few of us were alive back then. Exactly 70 years ago, March 31, 1951, the first commercial computer shipped. You might assume that the first computer was shipped...
    0 Comments
    Tags:
    first computer | univac
  • Shailly
    (P)SpiceItUp: Generating ISO 7637-2 Standard Pulse 2a in PSpice A/D
    By Shailly | 30 Mar 2021
    Many times, you would have required to create a standard pulse waveform that can be used for testing devices as per the industry standard. One good example is to simulate the ISO 7637-2 transient at the schematic design stage. This practice ensures t...
    0 Comments
    Tags:
    17.4 | OrCAD Capture | PSpiceA/D | Capture CIS | (P)SpiceItUp | 17.4-2019 | OrCAD
  • Jommy
    Library Characterization Tidbits: Define Measurements to Suit Your Characterization Requirements
    By Jommy | 30 Mar 2021
    Do you have a requirement to specify measurements that are not default while performing memory characterization? Liberate MX has a solution for you.
    0 Comments
    Tags:
    memory characterization | define_measure | Liberate MX | Library Characterization Tidbit | Liberate Characterization Portfolio
  • Paul McLellan
    The New Intel Foundry Services
    By Paul McLellan | 30 Mar 2021
    Yesterday, in my post Intel IDM 2.0 , I gave a summary of Pat Gelsinger's presentation last week on... well, everything he is doing as CEO of Intel after not much more than a month in the job—somehow I think that he's been thinking about...
    0 Comments
    Tags:
    Intel | intel custom foundry | intel foundry services
  • Steve PDK Lee
    Virtuoso Meets Maxwell:为什么没有提到引线键合IC?
    By Steve PDK Lee | 29 Mar 2021
    当今的许多模拟,RF和混合信号设计都要求在同一模组内部集成多个不同工艺的IC,以实现所需的性能目标。设计师使用异构器件集成方法能够获得单片IC (SoC) 设计上不容易达到的结果。与此同时对设计师而言,异构集成也是全新的挑战。
    0 Comments
    Tags:
    Chinese blog | ICADVM18.1 | Co-Design | Virtuoso System Design Environment | Virtuoso RF Solution | Wirebond | Electromagnetic analysis | Virtuoso | Custom IC Design | Allegro
  • Paul McLellan
    Intel IDM 2.0
    By Paul McLellan | 29 Mar 2021
    You've probably read in the press that Intel's new CEO, Pat Gelsinger, laid out his vision for Intel's future last week. You probably also know that, as he put it, "I've spent four decades in this industry, three of them here at ...
    0 Comments
    Tags:
    Intel | icf | idm 2.0 | intel custom foundry | foundry
  • Stefan Wuensche
    Spectre Tech Tips: Detecting Leakage Path Current Hotspots
    By Stefan Wuensche | 28 Mar 2021
    In circuit design, wrong connectivity may cause undesired leakage paths that may result in current hotspots. These current hotspots can be quickly identified with Spectre’s dynamic design checks. This blog describes how to use the Spectre design checks...
    0 Comments
    Tags:
    Dynamic design checks | Spectre design checks | leakage path detection | Spectre | dyn_dcpath | dyn_subcktpwr
  • Sarita Sharma
    Pegasus: Get Your Wings: Virtuoso/Pegasus In-Design Signoff
    By Sarita Sharma | 26 Mar 2021
    The beauty of Pegasus is that it doesn’t only work excellently in standalone mode but also seamlessly integrates with other tools such as the industry-standard Virtuoso custom/analog platform and enables users to complete advanced-node DRC in h...
    0 Comments
    Tags:
    Pegasus Verification System | Interactive SignOff Fill | pegasus | Pegasus Interactive | Density analysis | design for manufacturing
  • Paul McLellan
    Stopping Online Fraud
    By Paul McLellan | 26 Mar 2021
    I attended a webcast on Anti-Fraud organized by the RSA Conference in the leadup to the conference itself. It will be virtual, of course, and it will be held from May 17 to 20. If any aspect of your job involves security, or you are just interested, ...
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    Tags:
    security | ransomware | rsa
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