Cadence Blogs

BoardSurfers: Installation Know-How: Six Things You Need to Know Before Installing Cadence OrCAD and Allegro Products on Windows

By Shikha Jain | 4 Aug 2020

Installation of software applications depends upon certain factors such as system configuration, the number of files getting installed, and network speed. Installation time is influenced by a change in any of these elements and hence individual...

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Allegro OrCAD Installer | OrCAD | Allegro
IC Packagers: Removing and Replacing an Area of a Design

By Tyler | 4 Aug 2020

If you ever have the need to remove an area of your design, you may find it to be a more complex process than you would think. Shapes in that area will, if you select them with show element, want to pick up the entire shape. That may extend well outs...

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IC Package | Allegro Package Designer | 17.4-2019
Accellera Functional Safety

By Paul McLellan | 4 Aug 2020

This is my last post about DAC 2020. During DAC Accellera had a workshop about functional safety. In case you don't know, Accellera has a relatively new working group (WG) on Functional Safety. The chair is Cadence's Alessandra Nardi, who coi...

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automotive | functional safety | Accellera | fusa
Custom IC, Analog, and RF Design Training Deep Dive: Part 2

By Kira Jones | 3 Aug 2020

Let’s continue exploring the training courses related to Custom IC, Analog, and RF Design. We’re going to be introducing some new courses and some new tools in these training recommendations. It is recommended that you start with Custom I...

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Europractice | Cadence Academic Network | CMC Microsystems | Virtuoso | online training | university program
DAC 2020: Chips in 2030

By Paul McLellan | 3 Aug 2020

In 2015, soon after I rejoined Cadence, I went to IEDM, the International Electron Devices Meeting. That year it was in Washington DC. I paid for most of the trip myself since I'd already booked the flights and hotels months in advance to get goo...

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57dac | DAC | Design Automation Conference
Virtuosity: Analog Design Environmentにおけるポストレイアウト関連の機能強化トップ３

By Custom IC Japan | 2 Aug 2020

今日のブログでは、ポストレイアウトフローの最新の機能強化について説明します。これらの機能強化により、回路図とポストレイアウトの名前のマッピング、端子電圧のプロット、DSPFファイルのスイープなど、長年の問題の多くが解決されます。このブログは、 Virtuoso®ADE Assembler 、 Virtuoso®ADE Explorer および Virtuoso® Visualization and Analysis のリリースされたばかりの機能をカバーするために、週に2回（火曜日と...

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ADE Explorer | post-layout | DSPF | Virtuoso Analog Design Environment | postlayout | Virtuosity | japanese blog | ADE Assembler
Virtuoso Meets Maxwell: How Come There is No Mention of Wirebonded ICs?

By Steve PDK Lee | 2 Aug 2020

Hello and welcome to Virtuoso Meets Maxwell. If you are a regular reader you might be thinking to yourself, “There’s not a lot about wirebonds in the Virtuoso RF Solution and I’m interested in wirebond support.” That’s a great observation and it’s time...

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ICADVM18.1 | Co-Design | Virtuoso System Design Environment | Virtuoso RF | Wirebond | Electromagnetic analysis | Virtuoso | Custom IC Design | Allegro
Sunday Brunch Video for 2nd August 2020

By Paul McLellan | 2 Aug 2020

www.youtube.com/watch Made in "Indonesia" (camera me) Monday: Open Source Hardware Tuesday: DAC 2020: The State of the Industry Wednesday: DAC 2020: Open-Source EDA Thursday: Recruiting and Onboarding during WFH Friday: DAC 2020: TSMC ...

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sunday brunch
如何在PCB设计中解决最新的PCIe 信号完整性挑战

By Sigrity | 1 Aug 2020

图 1：基于 PCIe 的高性能显卡为了应对计算密集型工作负载，数据中心行业领域趋势正在向异构计算发展。该趋势同时推动着相应软件解决方案的开发，以便在具有不同核心和内存配置的多台计算机之间分配工作负载。伴随着高速计算而来的是对高速数据传输的需求：PCIe 总线是一种针对数据传输的关键性促成技术，其最新一代标准（4.0/5.0）大大提升了带宽并降低了延迟。尽管从数据吞吐量的角度来看这很有吸引力，但是这些性能方面的提升也带来了巨大的信号完整性（SI）设计挑战。为了应对 PCIe 4.0/5.0....

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Serial link analysis | SI | Chinese blog | 并行链路 | 误码率 | PCIe | 中文 | 通道仿真 | SerDes | Sigrity | Clarity 3D Solver | PCI-SIG | clarity
My Life at Cadence Video Series: Alessandra Nardi

By Mary Kasik | 31 Jul 2020

Cadence recently interviewed five of our amazing women engineers for a new video series titled “My Life at Cadence”! This fifth video features Alessandra Nardi, software engineering group director, Automotive Solutions...

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Insights on Culture | inclusion | Culture | STEM | cadence | my life at cadence | women
DAC 2020: TSMC Keynote

By Paul McLellan | 31 Jul 2020

The opening keynote at DAC was TSMC's Chief Scientist Philip Wong. That's clearly not nearly enough work, so he's a professor at Stanford, too. As I said in my post DAC Preview 2020 , I've seen a version of this presentation befor...

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57dac | DAC | TSMC | Design Automation Conference
BoardSurfers: Allegro In-Design Impedance Analysis：配線済みデザインをすばやくスクリーニング

By SPB Japan | 30 Jul 2020

すべての配線信号トレースを解析せずにプリント基板(PCB)を製造したことがありますか?ほとんどの設計者は「はい、いつも」と言うでしょう。トレースの幅と間隔はコンストレイントによって設定されており、多くの設計者は、これらのコンストレイントが設計に必要なマージン内のインピーダンス値に収まることを確認する時間がありません。基板上の高速トレースは最も慎重にレイアウトされていますが、残りのトレースは、ルーティング後に検査なしで製造に送られることがよくあります。 Sigrity ハイブリッドソ...

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PCB | PCB Editor | japanese blog
Virtuosity: In the Line of Veri-Fire - Episode 3

By Team ADE Verifier | 30 Jul 2020

Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso ADE Verifier and learn about its various whys and hows. In this series, Dr. Walter Hartong, a Product Engineering Architect at Cadence, will be answering some frequently...

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verifier | Analog Design Environment | Cadence blogs | ICADVM18.1 | custom/analog | Analog Coverage | ade suite | Analog Simulation | verification plan | custom IC simulation | analog | ADE | analog verification | Mixed-Signal | Virtuoso | Virtuosity | ADE Blog Series | FAQ | implementations | analog design | Custom IC Design | requirements | Custom IC | ADE Verifier | IC6.1.8 | Assembler | Verifier new feature | custom design technology | ADE Assembler | verification
It May Sound Unbelievable, But Do You Know You Can Relax While Analyzing Timing Results in Genus? Want to Check?

By Neha Joshi | 30 Jul 2020

Gone are the days when analyzing timing reports of the design used to take hours! We understand, your designs are complex and so is timing analysis. We cannot change the design, but we have made the timing analysis process easier for you during the synthesis...

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Analysis | Logic Design | Synthesis | scripting | timing
Liberate Characterization Tidbits: Deconstructing the Mechanics of Liberate MX Constraint Probing

By Neha Garhwal | 30 Jul 2020

Thinking about how Liberate MX characterizes the constraint arcs, how the probe locations are picked up by the tool, what are the various controls associated with probing? Read the blog to find the answers.

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worst-case probing | spectre aps | constraint probes | memory characterization | Spectre XPS | signal propagation | autoprobing | Liberate MX | Library Characterization Tidbit | debug report | Digital Implementation | automatic constraint probing | Liberate Characterization Portfolio | sequential partition
Recruiting and Onboarding During WFH

By Paul McLellan | 30 Jul 2020

My son has just been recruited into a new job in New York. He told me that it is a weird experience being recruited and starting in a company during the work-from-home (WFH) era. He doesn't know anyone, he hasn't met any of his co...

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onboarding | wfh | recruiting
IC Packagers: ボンドフィンガー・ソルダーマスク開口部の新しいオプション

By SPB Japan | 30 Jul 2020

ワイヤーボンドパッケージを設計する場合、パッケージ基板層のボンドフィンガーとリングはソルダーマスク層を通して露出させる必要があります。そうでければ、ワイヤーをそれらに結合することはかなり難しくなります。以前に “バウンドレスバウンティオブバウンディングシェイプ” (バウンディングシェイプの際限なき恩恵)” で Create Bounding Shape ツールについて話しました。ボンドフィンガーには、ソルダーマスクレイヤーを介した露出に関して、いくつか...

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17.4 | APD | japanese blog
IC Packagers: “バウンドレスバウンティオブバウンディングシェイプ” (バウンディングシェイプの際限なき恩恵)

By SPB Japan | 30 Jul 2020

この英文タイトルはまるで早口言葉ですね。早口で3回繰り返せますか？さて、今回のトピックスはAllegro® Package Designer及びSiP LayoutのShapesメニューにある"Create Bounding Shapes"ツールです。この機能について最初にお話したのは、実は数年前のことです。このコマンドの歴史に興味がおありでしたら、こちらのリンク(※英文)からその時の記事をご覧いただけます。このコマンドが最初にツールに追加された背景は、とあるお客様...

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17.4 | APD | japanese blog
The Returnship Journey: Part 2

By Ale Costa | 29 Jul 2020

Sharon Munoz’s Journey Stepping away from an engineering career to focus on caring for family can be a tough decision, but it doesn’t have to be the end of a career. New returnship programs, like the one offered by Cadence, provide a gre...

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inclusion | GPTW | women | returnship
Quickly View Schematic Designs, Boards, and IC Packages for Free Using Cadence PCB Viewers 2019

By AllegroReleaseTeam | 29 Jul 2020

Do you want to quickly view a schematic, layout, or IC package without installing the complete OrCAD product suite? Get read-only access to design data created in OrCAD Capture, PCB Editor, Allegro Package Designer Plus? With 17.4-2019 HotFix...

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OrCAD Capture | APD | PCB Editor | Allegro Package Designer | PCB design and layout | 17.4-2019
DAC 2020: Open-Source EDA

By Paul McLellan | 29 Jul 2020

The Department of Defense (and actually much of aerospace in general) is in an especially difficult place as regards access to silicon. Their production volumes are so low. This means they don't get great pricing from foundries, especially as mo...

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57dac | DAC | dac2020 | open source eda | openroad | posh | darpa
IC Packagers: Plating Bars versus Edge Connections

By Tyler | 28 Jul 2020

I think every traditional package designer understands what a plating bar is and the purpose it serves. There to provide electric current during the manufacturing process, each net is connected out to the perimeter of the BGA, which allows for the cu...

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Allegro Package Designer | 17.4-2019 | Allegro
DAC 2020: The State of the Industry

By Paul McLellan | 28 Jul 2020

Monday was the first day of DAC, the Design Automation Conference. Of course, like everything else it was fully virtual. Having been in EDA for nearly 40 years, my usual experience at DAC was not being able to walk more than about ten feet without ru...

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57dac | Design Automation Conference
Start Your Engines: CLIPSを使ってSoC検証用にポータブルなVirtuoso IPを生成する

By Custom IC Japan | 28 Jul 2020

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。ミックス...

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mixed signal design | AMS Designer | Mixed Signal Verification | Virtuoso | axum | mixed signal | japanese blog | analog/mixed signal | avum
Start Your Engines:デジタル機能検証フローのためにAMS UNL IP をエクスポートする

By Custom IC Japan | 27 Jul 2020

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 IP再利...

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AMS | AMS Designer | AMS Verfication | Verilog-AMS | analog | Mixed Signal Verification | analog/mixed-signal | Virtuoso | RNM | japanese blog | mixed-signal design | wreal | mixed-signal solution | verification