<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/atom.xsl" media="screen"?><feed xmlns="http://www.w3.org/2005/Atom" xml:lang="en-US"><title type="html">Artificial Intelligence (AI)</title><subtitle type="html" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/atom</id><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence" /><link rel="self" type="application/atom+xml" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/atom" /><generator uri="http://telligent.com" version="13.0.4.37021">Telligent Community (Build: 13.0.4.37021)</generator><updated>2026-03-30T10:00:00Z</updated><entry><title>Agentic AI for Design Verification and Debug</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/agentic-ai-for-design-verification-and-debug" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/agentic-ai-for-design-verification-and-debug</id><published>2026-10-29T05:00:00Z</published><updated>2026-10-29T05:00:00Z</updated><content type="html">Each new generation in chip design makes chip verification more complex. Today, verification activities consume &lt;a href="https://community.cadence.com/cadence_blogs_8/b/fv/posts/why-llms-are-the-best-thing-to-happen-to-chip-design" rel="noopener noreferrer" target="_blank"&gt;60-70% of the effort in chip development.&lt;/a&gt;

Better methodologies, more automation, and additional compute have helped. Even with those adva...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/agentic-ai-for-design-verification-and-debug"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364489&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Vinod Khera</name><uri>https://community.cadence.com/members/vinod-khera</uri></author><category term="agentic ai" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/agentic%2bai" /><category term="debug" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/debug" /><category term="AI in chip design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bin%2bchip%2bdesign" /><category term="ChipStack AI Super Agent" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ChipStack%2bAI%2bSuper%2bAgent" /><category term="AI" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI" /><category term="verification" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/verification" /></entry><entry><title>Who Signs the Tapeout? Ziyad Hanna on AI Chip Design – Wearing Flip-Flops</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/who-signs-the-tapeout-ziyad-hanna-on-ai-chip-design-wearing-flip-flops" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/who-signs-the-tapeout-ziyad-hanna-on-ai-chip-design-wearing-flip-flops</id><published>2026-10-27T18:00:00Z</published><updated>2026-10-27T18:00:00Z</updated><content type="html">
An AI agent writes the RTL, builds the testbench, runs the regressions, and closes coverage. Then an engineer signs the tapeout. What exactly is that engineer signing?
Ziyad Hanna, Corporate Vice President of R&amp;amp;D and Strategic Head of AI at Cade...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/who-signs-the-tapeout-ziyad-hanna-on-ai-chip-design-wearing-flip-flops"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364476&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Corporate</name><uri>https://community.cadence.com/members/corporate</uri></author><category term="ChipStack" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ChipStack" /><category term="Wearing Flip-Flops" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Wearing%2bFlip_2D00_Flops" /><category term="Ziyad Hanna" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Ziyad%2bHanna" /><category term="AI Super Agents" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bSuper%2bAgents" /><category term="ChipStack AI Super Agent" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ChipStack%2bAI%2bSuper%2bAgent" /></entry><entry><title>fJscaler, GF, and Cadence Collaborate to Scale Optical Interconnects for AI</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/fjscaler-gf-and-cadence-collaborate-to-scale-optical-interconnects-for-ai" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/fjscaler-gf-and-cadence-collaborate-to-scale-optical-interconnects-for-ai</id><published>2026-10-27T17:00:00Z</published><updated>2026-10-27T17:00:00Z</updated><content type="html">Unified EIC/PIC Co-Design and Strategic Foundry Collaboration Helps fJscaler Develop Advanced Optical Engines for AI Infrastructure
&lt;a href="https://www.fjscaler.com/"&gt;fJscaler&lt;/a&gt; is named after a unit of energy so small that it takes a quadrillion of them to make a single joule. That is ...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/fjscaler-gf-and-cadence-collaborate-to-scale-optical-interconnects-for-ai"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364478&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Corporate</name><uri>https://community.cadence.com/members/corporate</uri></author><category term="Cadence Oncloud" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Cadence%2bOncloud" /><category term="interconnects" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/interconnects" /><category term="featured" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/featured" /><category term="gf" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/gf" /><category term="GlobalFoundries" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/GlobalFoundries" /><category term="AI" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI" /></entry><entry><title>What Can Agentic AI Super Agents Actually Do for Me?</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/what-can-agentic-ai-super-agents-actually-do-for-me" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/what-can-agentic-ai-super-agents-actually-do-for-me</id><published>2026-10-22T17:00:00Z</published><updated>2026-10-22T17:00:00Z</updated><content type="html">
As chip and system designs grow more complex, engineering teams face increasing pressure to meet demanding developmentgoals without a proportional increase in engineering capacity. Time spent coordinating workflows and repeating tasks across design,...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/what-can-agentic-ai-super-agents-actually-do-for-me"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364475&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Reela Samuel</name><uri>https://community.cadence.com/members/reela-samuel</uri></author><category term="AuraStack AI Super Agent" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AuraStack%2bAI%2bSuper%2bAgent" /><category term="featured" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/featured" /><category term="agentic ai" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/agentic%2bai" /><category term="LLM" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/LLM" /><category term="AI in chip design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bin%2bchip%2bdesign" /><category term="InnoStack" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/InnoStack" /><category term="ChipStack AI Super Agent" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ChipStack%2bAI%2bSuper%2bAgent" /><category term="ai in eda" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ai%2bin%2beda" /><category term="AI/ML" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI_2F00_ML" /><category term="Super Agents" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Super%2bAgents" /><category term="ViraStack" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ViraStack" /></entry><entry><title>Accelerating Digital Implementation and Signoff with InnoStack AI Super Agent</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/agentic-ai-for-digital-implementation-and-signoff" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/agentic-ai-for-digital-implementation-and-signoff</id><published>2026-10-22T04:30:00Z</published><updated>2026-10-22T04:30:00Z</updated><content type="html">Modern SoC implementation involves more interdependent trade-offs than teams can explore manually. As chip and system complexity grow, digital implementation closure becomes increasingly difficult to coordinate, since it is rarely achieved through a ...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/agentic-ai-for-digital-implementation-and-signoff"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364472&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Vinod Khera</name><uri>https://community.cadence.com/members/vinod-khera</uri></author><category term="featured" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/featured" /><category term="agentic ai" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/agentic%2bai" /><category term="AI in chip design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bin%2bchip%2bdesign" /><category term="InnoStack" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/InnoStack" /><category term="Digital Implementation" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Digital%2bImplementation" /><category term="AI Super Agents" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bSuper%2bAgents" /><category term="ai in eda" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ai%2bin%2beda" /><category term="signoff" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/signoff" /><category term="AI" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI" /></entry><entry><title>Agentic AI for PCB and Advanced Packaging Design</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/agentic-ai-for-pcb-and-advanced-packaging-design" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/agentic-ai-for-pcb-and-advanced-packaging-design</id><published>2026-10-15T15:00:00Z</published><updated>2026-10-15T15:00:00Z</updated><content type="html">
As AI workloads grow, more engineering challenges extend beyond the chip itself to the package that brings compute, memory, power, and cooling together. The HBM4 standard is designed to increase memory bandwidth, while evolving stacking requirements...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/agentic-ai-for-pcb-and-advanced-packaging-design"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364451&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Reela Samuel</name><uri>https://community.cadence.com/members/reela-samuel</uri></author></entry><entry><title>How to Verify and Signoff AI-Generated Design Data</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/how-to-verify-and-sign-off-ai-generated-design-data" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/how-to-verify-and-sign-off-ai-generated-design-data</id><published>2026-10-07T09:35:00Z</published><updated>2026-10-07T09:35:00Z</updated><content type="html">
An &lt;a href="https://www.cadence.com/en_US/home/explore/agentic-ai.html"&gt;agentic AI&lt;/a&gt; system can generate and iterate through design changes at a scale and speed that conventional workflows cannot. It can generate RTL, propose an ECO, modify a constraint, create a verification property, or explore an implementation opti...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/how-to-verify-and-sign-off-ai-generated-design-data"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364435&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Reela Samuel</name><uri>https://community.cadence.com/members/reela-samuel</uri></author><category term="agentic ai" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/agentic%2bai" /><category term="AI in chip design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bin%2bchip%2bdesign" /><category term="NVIDIA openshell" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/NVIDIA%2bopenshell" /><category term="EDA" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/EDA" /><category term="autonomous" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/autonomous" /><category term="AI Super Agents" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bSuper%2bAgents" /><category term="ChipStack AI Super Agent" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ChipStack%2bAI%2bSuper%2bAgent" /><category term="signoff" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/signoff" /><category term="AI/ML" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI_2F00_ML" /><category term="verification" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/verification" /></entry><entry><title>Autonomy Levels for Design Agents: L1 to L5 Explained</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/from-optimization-to-full-autonomy-in-eda" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/from-optimization-to-full-autonomy-in-eda</id><published>2026-09-23T06:10:00Z</published><updated>2026-09-23T06:10:00Z</updated><content type="html">&lt;a href="https://www.cadence.com/en_US/home/explore/agentic-ai.html" rel="noopener noreferrer" target="_blank"&gt;Agentic AI&lt;/a&gt; plays an important role in chip and system design, but not every &amp;ldquo;agentic&amp;rdquo; capability has the same degree of autonomy. In practice, autonomy is not binary. It is a progression from AI that optimizes bounded engineering tasks to...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/from-optimization-to-full-autonomy-in-eda"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364398&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Vinod Khera</name><uri>https://community.cadence.com/members/vinod-khera</uri></author><category term="agentic ai" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/agentic%2bai" /><category term="Design Agents" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Design%2bAgents" /><category term="AI in chip design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bin%2bchip%2bdesign" /><category term="AI Super Agents" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bSuper%2bAgents" /><category term="AI" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI" /></entry><entry><title>What Agentic AI Actually Does in EDA</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/what-agentic-ai-actually-does-in-eda" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/what-agentic-ai-actually-does-in-eda</id><published>2026-09-16T16:25:00Z</published><updated>2026-09-16T16:25:00Z</updated><content type="html">
Electronic design automation (EDA) has always been about turning engineering intent into a sequence of computational operations. An engineer defines a design, establishes constraints, runs analysis, studies the results, makes changes, and runs the t...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/what-agentic-ai-actually-does-in-eda"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364370&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Reela Samuel</name><uri>https://community.cadence.com/members/reela-samuel</uri></author><category term="artificial intelligence" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/artificial%2bintelligence" /><category term="agentic ai" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/agentic%2bai" /><category term="LLM" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/LLM" /><category term="AI in chip design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bin%2bchip%2bdesign" /><category term="AI-Driven Design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI_2D00_Driven%2bDesign" /><category term="EDA" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/EDA" /><category term="AI for design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bfor%2bdesign" /><category term="ai in eda" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ai%2bin%2beda" /><category term="AI/ML" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI_2F00_ML" /></entry><entry><title>AI-Driven Simulation for Faster and Confident Thermal Design</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/ai-driven-simulation-for-faster-and-confident-thermal-design" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/ai-driven-simulation-for-faster-and-confident-thermal-design</id><published>2026-09-03T06:00:00Z</published><updated>2026-09-03T06:00:00Z</updated><content type="html">This blog is based on the presentation delivered by Jiwon Yu from Celestica titled &amp;lsquo; Validating and Accelerating Thermal Design Optimization using AI-Driven Simulation&amp;rsquo; at CadenceLIVE Silicon Valley 2026

As thermal architecture grows in ...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/ai-driven-simulation-for-faster-and-confident-thermal-design"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364355&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Veena Parthan</name><uri>https://community.cadence.com/members/veena-parthan</uri></author><category term="CFD" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/CFD" /><category term="Celestica" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Celestica" /><category term="Optimality Intelligent System Explorer" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Optimality%2bIntelligent%2bSystem%2bExplorer" /><category term="Celsius EC Solver" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Celsius%2bEC%2bSolver" /><category term="AI-driven simulation" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI_2D00_driven%2bsimulation" /><category term="Electronics cooling" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Electronics%2bcooling" /><category term="AI for design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bfor%2bdesign" /></entry><entry><title>You'll Still Do the Work—You Just Won't Do the Boring Part</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/you-ll-still-do-the-work-you-just-won-t-do-the-boring-part" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/you-ll-still-do-the-work-you-just-won-t-do-the-boring-part</id><published>2026-07-13T16:00:00Z</published><updated>2026-07-13T16:00:00Z</updated><content type="html">Agentic AI is about to change your flow. Here&amp;#39;s what actually shifts&amp;mdash;and why the engineers who move first will pull away from the ones who wait.
It&amp;#39;s 11 p.m. The overnight regression failed&amp;mdash;again&amp;mdash;and you&amp;#39;re three hours into triaging...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/you-ll-still-do-the-work-you-just-won-t-do-the-boring-part"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364248&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Corporate</name><uri>https://community.cadence.com/members/corporate</uri></author><category term="artificial intelligence" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/artificial%2bintelligence" /><category term="featured" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/featured" /><category term="agentic ai" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/agentic%2bai" /><category term="NVIDIA" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/NVIDIA" /><category term="AI for design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bfor%2bdesign" /></entry><entry><title>The Feedback Loop Is the Moat</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/the-feedback-loop-is-the-moat-480749506" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/the-feedback-loop-is-the-moat-480749506</id><published>2026-06-30T20:00:00Z</published><updated>2026-06-30T20:00:00Z</updated><content type="html">Every verification and design team I talk to is building agents right now. The demos are genuinely impressive: point an LLM at some RTL, ask it to write assertions or close coverage or root-cause a failure, and it produces something that looks right....(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/the-feedback-loop-is-the-moat-480749506"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364224&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Hamid Shojaei</name><uri>https://community.cadence.com/members/hamid-shojaei</uri></author><category term="featured" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/featured" /><category term="AI in chip design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bin%2bchip%2bdesign" /><category term="GenAI" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/GenAI" /><category term="AI/ML" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI_2F00_ML" /></entry><entry><title>The Rise of the Autonomous Engineer</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/the-rise-of-the-autonomous-engineer" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/the-rise-of-the-autonomous-engineer</id><published>2026-06-01T05:30:00Z</published><updated>2026-06-01T05:30:00Z</updated><content type="html">Agentic AI in engineering has moved from concept to reality at remarkable speed. What began as isolated AI-assisted workflows is rapidly evolving into fully autonomous systems capable of reasoning, planning, and executing complex engineering tasks. A...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/the-rise-of-the-autonomous-engineer"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364176&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Corporate</name><uri>https://community.cadence.com/members/corporate</uri></author><category term="featured" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/featured" /><category term="agentic ai" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/agentic%2bai" /><category term="NVIDIA" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/NVIDIA" /><category term="AI-Driven Design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI_2D00_Driven%2bDesign" /><category term="AI for design" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI%2bfor%2bdesign" /><category term="Cadence AI Stack" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Cadence%2bAI%2bStack" /><category term="ChipStack AI Super Agent" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ChipStack%2bAI%2bSuper%2bAgent" /><category term="AI" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI" /><category term="Computex" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Computex" /></entry><entry><title>Reimagining Chip Design - From Spec to Signoff with Cadence AI Super Agents</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/reimagining-chip-design-from-spec-to-signoff-with-cadence-ai-super-agents" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/reimagining-chip-design-from-spec-to-signoff-with-cadence-ai-super-agents</id><published>2026-04-16T17:30:00Z</published><updated>2026-04-16T17:30:00Z</updated><content type="html">At CadenceLIVE Silicon Valley 2026, Cadence took a major step toward fully autonomous chip design&amp;mdash;introducing two powerful new AI Super Agents that complete an end-to-end chip design flow. The ViraStack AI Super Agent targets analog design and ...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/reimagining-chip-design-from-spec-to-signoff-with-cadence-ai-super-agents"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364089&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Corporate</name><uri>https://community.cadence.com/members/corporate</uri></author><category term="news story" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/news%2bstory" /><category term="SystemStack" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/SystemStack" /><category term="artificial intelligence" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/artificial%2bintelligence" /><category term="ChipStack AI SuperAgent" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ChipStack%2bAI%2bSuperAgent" /><category term="ChipStack" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ChipStack" /><category term="featured" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/featured" /><category term="agentic ai" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/agentic%2bai" /><category term="InnoStack" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/InnoStack" /><category term="Mental Model" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/Mental%2bModel" /><category term="3DStack" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/3DStack" /><category term="AgentStack" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AgentStack" /><category term="AI" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI" /><category term="ViraStack" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ViraStack" /></entry><entry><title>Cadence Brings Chip Verification to the Next Level with AI Agents</title><link rel="alternate" type="text/html" href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/cadence-brings-chip-verification-to-the-next-level-with-ai-agents" /><id>https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/cadence-brings-chip-verification-to-the-next-level-with-ai-agents</id><published>2026-03-30T17:00:00Z</published><updated>2026-03-30T17:00:00Z</updated><content type="html">By Karl Freund of &lt;a href="https://cambrian-ai.com"&gt;Cambrian-AI Research&lt;/a&gt;, sponsored by Cadence
&amp;nbsp;
Introduction
The chip design process has become a linchpin in the global digital economy as cloud computing and artificial intelligence grow rapidly. The economic impact is huge. For...(&lt;a href="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/cadence-brings-chip-verification-to-the-next-level-with-ai-agents"&gt;read more&lt;/a&gt;)&lt;img src="https://community.cadence.com/aggbug?PostID=1364050&amp;AppID=136&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>Corporate</name><uri>https://community.cadence.com/members/corporate</uri></author><category term="artificial intelligence" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/artificial%2bintelligence" /><category term="ChipStack AI SuperAgent" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ChipStack%2bAI%2bSuperAgent" /><category term="ChipStack" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/ChipStack" /><category term="featured" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/featured" /><category term="agentic ai" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/agentic%2bai" /><category term="AI" scheme="https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/archive/tags/AI" /></entry></feed>