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The Electronic System Design Alliance (fka EDAC) has been organizing evening meetings every 6 months or so, under the auspices of the emerging companies. These are hosted by Jim Hogan. The latest one took place last week at Cadence and was about two organizations. SiFive, which is truly and emerging company, and the RISC-V Foundation, which as a non-profit is pushing the boundaries a little.
I have covered RISC-V extensively, and they seem to have become a resource for people getting up to speed:
The three panelists were:
Rick was first up to be interviewed. The RISC-V foundation formally got off the ground in August 2015 so just 18 months ago. It has been sitting on a rocket. One of the important things that the foundation does is organize workshops every 6 months. Jim said he attended the 4th workshop (at MIT). I attended the 5th a couple of months ago. The 6th will be hosted by NVIDIA in Shanghai next May. Rick warned it would sell out. I hope to be there.
At the last one, over 100 companies were represented, with over 300 attendees (and not just me from Cadence). There are currently around 50 member companies, but they all joined as charter members, on trust, since there was no membership agreement. That now exists, so new non-charter members will be allowed to join.
Rick was asked what the foundation owns and the answer is—nothing. The only real thing is that they administer trademark licenses. To give you some idea of how nobody really expected this to become so big so fast, those trademarks are actually personally owned by Krste Asańovic, who was the leader of the team that developed the RISC-V ISA (and is currently on leave of absence at SiFive). The ISA is totally open—if you want to design with it, then go ahead. But if you want to call it RISC-V, then you need to pass the compliance tests and get a license.
Rick says, "I'm constantly asked—where’s my processor core, Mr. Foundation guy? But we don’t do that. Some members have proprietary cores, some open source."
It turns out that Jim first met Yunsup years ago (apparently when he was in the 8th year of his Ph.D.). Reading between the lines, Yunsup was trying to raise money for a processor company that eventually became SiFive. “Good luck with that,” was Jim's opinion and he passed on investing, which he said was an error.
He said the roots of RISC-V go back to 2008 when they tried to build a couple of things on SPARC and MIPS since they could leverage the existing ecosystem. But this turned out to be much more complex than expected because when you port the existing ecosystem, you find it won't work because there are bugs in the processors, and operating systems like Linux have been fixed to get around them. So that means that if you want to run the code, you need to implement the same bugs. It reminded me of my time running engineering at Ambit when we had a switch in the tool for whether we should accept incorrect Verilog because other synthesis tools did, or whether we should be strict about the language.
So one lesson of that experience was that there was no way they were going to implement ARM or x86 in practice with a team of six people (not to mention, no lawyers). So they started on RISC-V. It's called RISC-V because David Patterson implemented the original RISC 1 and RISC 2. Then, the next two were called SOAR and SPUR (which he admits was a mistake).
So they designed the ISA, came up with compiler support, built 28nm chips that ran at 1.5GHz. After a couple of years, they put the specs on the web without knowing who, if anyone, was using them—until they started getting messages saying, “Will you guys stop changing things, we're trying to run courses / do grad work / whatever.”
The Linley Group just picked RISC-V as the best technology of 2016, having organized a sort of debate at the last processor conference as to whether it would succeed. (My answer? Yes, unless you set the bar so high that all other ISAs must die for it to count as success.)
MicroSemi doesn't exactly count as an emerging company, but the RISC-V activity within it does. RISC-V first came on his radar when some guy said he'd implemented a RISC-V processor on one of MicroSemi's arrays. Soon he was in Berkeley talking to the team. He said that things have gone really fast in MicroSemi because they specialize in security. ARM and x86 were developed before security was an issue and are backfilling, but now lots of secure work is going on using RISC-V. They have real contracts with companies and government organizations to produce RISC-V-based security products. But if he told us too much, they wouldn't be secure.
The first one was for a space project, and they picked SiFive to do the implementation, rather than getting their own team up to speed.They were SiFive's first customer.
The next topic was raising money. Jim asked how they did it. Yunsup said the more they knew about hardware, the earlier they cut off the conversation. The record was two sentences (and that was a semiconductor processor guy, so it wasn't out of ignorance!). They met Sutter Hill in 2014 (famous for the early funding of NVIDIA 20 years ago, which was their last semiconductor investment). But partner there is a chip guy from Cisco—Stefan Dyckerhoff—and Juniper and he understood immediately. He said that he had every ISA in his engineering organization, and so having a single ISA has huge value. He had lots of people just dealing with different ISAs.
The SiFive business model is that lots of people are locked out of silicon. SiFive can do custom design and deliver chips. "We believe we can do it cheaper, quicker and more predictably than anyone else.” They have also been getting lots of calls to help with designs. Growing the RISC-V ecosystem is a big opportunity.
The traditional semiconductor business models take a lot of resources, so you have to pick the winners. But there aren't any $1B sockets anymore, so you can't easily pick the winners. The market is fragmented. SiFive wants to give everyone a chance. In a bit more detail, they will do a customer microcontroller platform and deliver 100 or so chips for under $100K.
System architects just don’t want to know all the stuff it takes to get to a chip. IoT nodes will mostly be older. It’s a question of $100K vs. $150M for a leading edge device. $100K is low enough for angel investors like me, Jim pointed out, getting out his checkbook.
Academia has basically switched. Patterson and Hennessy's books on computer architecture, which have been the standard texts forever, are being converted. The result: every CS/EE grad will already know and be familiar with RISC-V in a couple of years.
Yunsup summed up the opportunity succinctly: "For the first time ever, the thing that you learn and the thing that you use are the same".
In the beginning, they knew all the projects. Now nobody has a clue how much is going on and where— there is just too much. RISC-V is making hardware cool again because you can do innovation in processor hardware that has been effectively impossible outside the biggest companies for a decade or more. All big companies doing SoCs are trying to switch as fast as they can. (One public company is NVIDIA, which has said that all of their SoCs will contain a RISC-V control processor).
Rick told us of a meeting with a corporate fellow of a large computer company, convincing his company to get on board, who said, “If we do this right, we could be setting the computing platform for everything for the next 50 years.” Or as Krste likes to put it wryly, "Our modest goal is to become the industry standard for all computing devices."
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