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Paul McLellan
Paul McLellan
15 Jun 2022

HOT CHIPS 34 Preview

 breakfast bytes logohot chips 34 logo

Every Summer, one of the most interesting conferences I attend is HOT CHIPS. Often the presentations themselves are interesting since they describe some of the highest-performance chips that are either recently shipping or soon to be shipping. But also, the stream-of-consciousness aspect of seeing the commonality in many of the chips gives a real sense of important trends in the industry. For example, in 2019, it became obvious that for high-end designs that system-in-package (various forms of 3D and 2.5D packaging) was going to become widespread, if not ubiquitous. See my post HOT CHIPS: Chipletifying Designs for my take on it three years ago.

This year's HOT CHIPS is again going to be virtual, unfortunately. I say unfortunately because I much prefer the in-person experience. Somehow it is much easier to concentrate on a real person giving a real presentation compared to a pre-recorded presentation, what I call "talking PowerPoint."

HOT CHIPS 34 will take place from Sunday, August 21st, to Tuesday, August 23rd.

Tutorials

As usual, Sunday is taken up with two tutorials, one in the morning and one in the afternoon.

cxl logoThe morning tutorial this year is on CXL. This stands for Compute eXpress Link. You can read some background about it in my post Cadence and Intel Demonstrate CXL 1.1/2.0 Interoperability. The tutorial is split up into several sections:

  • CXL overview and evolution
  • CXL2/CXL3 coherency deep dive
  • Memory use cases and challenges
  • CXL3 Fabric introduction and use cases

Note that the presenters have not yet been announced.

mlir logoThe afternoon tutorial is on Heterogeneous Compilation in MLIR. For once, "ML" doesn't stand for machine learning! MLIR is Multi-Level Intermediate Representation.

  • Basic Concepts by Stella Laurenzo of Google
  • Code Generation by Harsh Menon of Nod.AI
  • ML Frontends and frameworks by Suraj Sudhir of Arm
  • CIRCT by Andrew Lenharth of SiFive and John Demme of Microsoft

I had not heard of CIRCT before, but it is the most relevant to the EDA industry (and Cadence, of course). Here are a couple of paragraphs to show why:

The EDA industry has well-known and widely used proprietary and open source tools. However, these tools are inconsistent, have usability concerns, and were not designed together into a common platform. Furthermore, these tools are generally built with Verilog (also VHDL) as the IRs that they interchange. Verilog has well-known design issues and limitations, e.g., suffering from poor location tracking support.

The CIRCT project is an (experimental!) effort looking to apply MLIR and the LLVM development methodology to the domain of hardware design tools. Many of us dream of having reusable infrastructure that is modular, uses library-based design techniques, is more consistent, and builds on the best practices in compiler infrastructure and compiler design techniques.

For more about CIRCT, see their website.

GPUs and HPC

Monday kicks off with a session on GPUs and HPC.

  • NVIDIA’s Hopper GPU: Scaling Performance by Jack Choquette & Ronny Krashinsky of NVIDIA
  • AMD Instinct MI200 Series Accelerator and Node Architectures by Alan Smith & Norman James of AMD
  • Intel’s Ponte Vecchio GPU: Architecture, System, and Software by Hong Jiang of Intel
  • Biren BR100 GPGPU: Accelerating Datacenter Scale AI Computing by Mike Hong & Lingjie Xu of Biren Technology

I wrote about Ponte Vecchio last year in my post HOT CHIPS: Two Big Beasts.

Integration Technologies

The second half of the morning is about various integration technologies.

  • Passage—A Wafer-Scale, Programmable Photonic Communication Substrate by Nicholas Harris of Lightmatter
  • Heterogeneous Integration Enables FPGA Based Hardware Acceleration for RF Applications by Tim Hoang of Intel
  • Enabling scalable application-specific optical engines (ASOE) by monolithic integration of photonics and electronics by Christoph Schulien of Ranovus
  • Scaling of Memory Performance and Capacity with CXL Memory Expander by Sung Joo Park of Samsung

pat gelsinger intelKeynote

The afternoon starts with a keynote from Pat Gelsinger, who I'm sure you already know is the CEO of Intel. His keynote is titled Semiconductors Run the World.

Academia

Following the keynote, there is a sort of catch-all category called "Academia."

  • HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces by Abhishek Bhattacharjee of Yale
  • Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs by Alfio Di Mauro of ETH Zurich
  • Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration by Kathleen Feng of Stanford
  • Arm Morello Evaluation Platform - Validating CHERI-based Security in a High-performance System by Richard Grisenthwaite of Arm

I wrote about CHERI and Morello in my post What Is a Capability? CAP, CHERI, and Morello.

Machine Learning

Tuesday kicks off with a session on machine learning (ML).

  • Groq Software-Defined Scale-out Tensor Streaming Multi-Processor by Dennis Abts of Groq
  • Boqueria - Next Generation At-Memory Inference Acceleration Device with 1,000+ RISC-V cores by Robert Beachler of Untether AI
  • DOJO: The Microarchitecture of Tesla’s Exa-Scale Computer by Emil Talpes of Tesla
  • DOJO - Super-Compute System Scaling for ML Training by Bill Chang of Tesla
  • Cerebras Architecture Deep Dive: First Look Inside the HW/SW Co-Design for Deep Learning by Sean Lie of Cerebras

I wrote about DOJO in my post NOT CHIPS: Tesla's Project Dojo. I wrote about the Cerebras "chip" when they presented last year, in the same post as Ponte Vecchio linked to above.

Network and Switches

The second half of the morning is networks and switches.

  • AMD 400G SmartNIC SOC “Versal Net” (placeholder name, real product name to be announced later) by Jaideep Dastidar of AMD
  • Juniper’s Express 5: A 28.8Tbps Network Routing ASIC and Variations by Chang-Hong Wu of Juniper
  • NVLink-Network Switch - NVIDIA’s Switch Chip for High Communication-Bandwidth SuperPODs by Alexander Ishii and Ryan Wells of NVIDIA

ganesh teslaKeynote

The second-day keynote is by Ganesh Venkataramanan of Tesla and is titled Beyond Compute - Enabling AI through System Integration.

ADAS and Grace

Another potpourri category:

  • NVIDIA’s Orin System-on-Chip by Michael Ditty of NVIDIA
  • NODAR 3D Vision System: Enabling Mass Production of Autonomous Vehicles by Leaf Jiang of NODAR
  • NVIDIA’s Grace CPU by Jonathon Evans of NVIDIA

Mobile and Edge Processors

Finally, the conference wraps up with a session on mobile and edge processors.

  • AMD Ryzen 6000 Series Processor by Jim Gibney of AMD
  • Meteorlake and Arrowlake: Intel Next Gen 3D Client Architecture Platform with Foveros by Wilfred Gomes of Intel
  • Dimensity 9000 – A Flagship SmartPhone SoC by Hugh Mair of MediaTek
  • Next-Generation Intel processor built for the edge – Intel Xeon D 2700 and 1700 by Praveen Mosur of Intel

Details

Full details on HOT CHIPS, including links for registration (open) are on the HOT CHIPS website.

 

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Tags:
  • CXL |
  • hotchips |
  • circt |
  • mlir |