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At the recent Chiplet Summit, there was a panel session on the last afternoon titled How to Make Chiplets a Viable Market. The panel was moderated by Meta's Ravi Agarwal, and the panelists were (from left to right in the photo):
Unusually, for a panel session, the room was completely full with lots of people standing at the back.
I think that this is one of the most interesting topics in the whole chiplet arena. I have no doubt that technical problems like chiplet die-to-die interfaces, creating good chiplet library formats, or improving testing for known-good-die will all be solved in time. But just what the chiplet business models will be remains foggy, to say the least. I've said before that the dream is to take an Intel CPU chiplet, an NVIDIA GPU chiplet, a Qualcomm modem chiplet, and an AMD/Xilinx FPGA chiplet, and put them all into the same system-in-package. We are a long way from that today!
The format was that each panelist spent a couple of minutes introducing themselves and showing a couple of slides. Then Ravi put up a slide with a few questions he'd already prepared. And then it was the audience's turn to ask questions of the panel.
I'll give my usual preamble to when I report on a panel. This is not verbatim what everyone said, it is me paraphrasing it. I put Q in front of each question to make them stand out. That means it is Ravi asking, or someone in the audience in the last section. I identify answers by the name of the company, so you don't have to remember who works for which company. Any remarks in square brackets are mine [and not something any of the panelists said].
Ventana: Everyone is excited about chiplets but today it is only done by large companies using their own chiplets. The challenge is whether multiple companies can use chiplets that work together? There is a variety of companies we work with as an ecosystem, so that proof point is here today.
Alphawave: There is a rule of conferences. If you have a conference and lots of people show up, then in five years you will have a market.
Marvell: An open chiplet market is a beautiful concept, but a few things are getting in the way. The dream is that you can walk through the market and fill your cart up. Today only vertically integrated, or vendor builds to spec but only for a limited number of chiplets and only trusted partners. This is very far from the dream of an open chiplet market. Is there an incremental step? How do we get there? The slide above shows the pros (green) and cons (red) for various approaches to a chiplet-based design.
NVIDIA: “Moore’s Law has died at the age of 51 after an extended illness…for now lawbreaking is going to be the new normal” Ars Technica. We need a solution that is applicable to smaller vendors.
Samsung: Chiplets as a solution is already here, but how do we move it to chiplets as a business or a marketplace? Interoperability can mean lots of proprietary things, but for a marketplace there has to be an open standard. For interfaces like PCIe we have "plugfest" events to ensure interoperability, and we will need something similar for die-to-die but I have no idea how that will really work. Packaging is going to be one of the toughest things.
Q: What is the market demand for chiplets in the next 5-10 years?
Marvell: For everything we do, everyone is looking for a way to use multichip systems to optimize their spend. This is all high-end infrastructure. We do single chips once in a while but it is becoming a rarity.
Ventana: Automotive ADAS solutions are so large “we have to split the die up anyway so we may as well start to work on these issues.” We want organic substrate so it is not limited to super-large super-expensive chips.
NVIDIA: Datacenter will be a $500B market in AI in two years, so there is a strong demand. Chiplets are the only way to go.
Samsung: I talk to a lot of customers, and the big guys claim that 50% of their designs today are chiplet-based (but they are vertically integrated). In 5-10 years, demand will be very high, but for everyone else, we need to build this ecosystem. The OSATs need to be ready, interface interoperability is a requirement (UCIe was announced but is not here yet). Open HBI has kind of disappeared, BoW [bundle of wires].
Q: What business models will address chiplets, and what is your experience with KGD [Known Good Die]?
Ventana: Someone owns the final design, and if you have a problem, you call your vendor. Not much different from IP. It is different, but there are models that exist.
AlpahWave: ASIC model is what we need at first. We are all now driving for standards to have more options. We make chiplets, and 5-10 years from now maybe you can go shopping with the shopping cart.
Marvell: We have experience with the “choose a trusted partner” model. How you enable multiple chiplets, each with its own test capability and KGD, is really a challenge when integrating from multiple sources. We need to find approaches that allow companies to share a lot more information without being worried about losing their intellectual property.
Samsung: For sure, it will be an evolution, but today it is a business negotiation. “You own the whole thing”. Today there is no standard model.
Q: How do we ensure the security of chiplets?
Marvell: Right now, the definition of security is that it is all within one SoC. But do you have security in just one chiplet? Or does everyone have their own? We need to get to the point where we can get multiple chips to behave as one in a secure manner. That technology doesn’t exist today.
NVIDIA: Datacenters have a lot of security requirements, and we need them to be secured within transit, when stored, when being computed on.
Alphawave: Even secure boot is an issue. Which chiplet is it supposed to be in? Where do you put it? Maybe we need a dedicated security chiplet?
Q: If a product has several chipsets, do you believe the end customer will see margin stacking?
Marvell: I already said “yes”. In my imaginary system I showed earlier, I wanted the best-in-class for each chiplet. And in that environment, I don’t see how we can avoid margin stacking. I would love to get to the point that a chiplet is like a packaged part and we hide just enough of the secret sauce. We have got used to the IP model and if chiplets become more like IP then we can see some evolution.
Ventana: I see chiplets enabling people to buy just what they want. If you are creating a solution specific to your needs, and if you are buying just what you need, it will be more cost-effective. This will offset some of the margin issues.
Alphawave: No more than today with foundry, IP, and so on. If you can buy an I/O chiplet that has been in 60 different products, then your costs should be lower. UCIe is like PCIe, you are just “plugging it in".
Q: What about software support? In a chiplet, there are microcontrollers to handle the boot or initialize the system, so what support should we provide to the end customer for the pieces of software attached to each subsystem?
Marvell: This is a problem with chipsets today. A vertically integrated company can invest in common APIs, and can do that on chiplet-based systems too. But this doesn’t work outside vertically integrated or build-to-spec. It makes die-to-die communication seem simple in comparison.
Ventana: We do this today. You have to figure out how to partition it, just like stitching together an SoC and giving a full software solution.
NVIDIA: This is a requirement to grow the chiplet ecosystem. When you have four or five companies working together, we don’t today have a common API framework.
Alphawever: Someone, unfortunately, doesn’t buy all the IP for me, and today we have to provide all the APIs from five different vendors and work out how to make all those APIs seamless to the customer. it is a challenge.
Samsung: WShen you ship your chiplet-based design to the end user, it should look the same as an SoC. It should look like “one big chip,” and we need to get to the point we do the software the same way we do for SoCs.
Q: Drawing parallels to CXL and chiplets is great. For CXL, we have a “fabric manager” for which there is no definition. In a heterogeneous world, that model will not hold. Is the definition of “fabric manager” going to be part of a multi-chiplet design?
NVIDIA: Fabrics are very important. The current CXL fabric only addresses one aspect, namely memory. It is not addressing peer-to-peer. CXL is still scaling up. staying within the rack. But we need to think about scaling out too. [rack-to-rack]
Marvell: Not all chiplet systems will be PCIe or CXL based. Can you rely on a defined standard for a fabric manager when they may want to communicate in a different way?
Q: (Google) We would love to see chiplets and I’m a big proponent. The physical form factor is a big difference from IP. How are we going to address that? Until we do it will be hard to build a marketplace.
Alphawave: There are different bump pitches, different numbers of lanes, and so on. All different, so how do you prioritize? Which one do you make first?
Marvell: There is no reasonable approach to standardizing form factors so that they will tile together nicely. There will be multiple die2die interface solutions that we will need too. The Tetris problem is incredibly difficult to solve.
Q: What about form factor?
Alpahwave: It is a tradeoff against time to market. You want two lanes but you get 16. You have 16 now, or you wait a year for two.
Samsung: It’s like FPGAs. They are never just the right size.
Marvell: When is the right time to create a chiplet? I fear right now we are so excited about chiplets we want to make everything into a chiplet, and that is already not right.
Alphawave: if your competition succeeds in going monolithic you will lose. Chiplets may not always be the answer.
Q: We talked a lot about disaggregation of large die. But what about smaller die, like something that might fit in your watch? Do they have the same values?
Marvell: There are lots of places you might make it.
NVIDIA: I don't work for Apple, but I've seen the teardowns of Apple Watch there is a motherboard on substrate architecture, so it is already chiplets.
Alphawave: Lots is going into smaller form factors.
Samsung: As you go smaller, the overhead on the interface becomes bigger. If it is being used in multiple applications and you can leverage it, fine. But going chiplets just for chiplets sake makes no sense.
Ventana: It is a no-brainer if it is a large data center chip. The lower limit is coming down, but maybe not all the way to $10.
Q (Achronix) Is there some sort of landscape? We get approached by people wanting to do chiplets, and often, they are inappropriate. Is there any academic research that shows the maturity of technology nodes, and what does the landscape look like so people can decide on which side of the breakeven point they are on?
Meta (Ravi): There is an OCP open cost model, which is the best thing that exists. It has 20 to 15 variables that you can choose from, and it is a good place to start.
Alphawave: We have a chart showing where the breakeven points are.
Samsung: I was involved n the open cost model, but it is high level since nobody is going to tell you the detailed costs. It is spreadsheet-based, so you can change things around.
Meta: They are planning to release a new version of the model soon.
Q: One of you mentioned earlier what the cost model going forward should be, and maybe the IP model is the same. As a one-man startup in the 1980s, I could buy standard parts for $10 or $20, and I thought that in the FPGA market, I could just buy these pieces of IP at that price point, too. But no, they were $100,000 each. The IP model for ASICs didn’t work for FPGA. Now chiplets are taking me back to my 1980s world. Will I be able to buy them for $10 or $20 and build a system?
Alphawave: The IP model works if you want to build your own chiplet. But for a chiplet itself, you buy the whole thing.
Marvell: That is the dream, you don’t have to pay for advanced technology masks, and the associated mask costs. The mask costs are so much more than the IP costs.
Ventana: You don’t need to spend a fortune to license an IP core, you can just buy the chiplet.
Samsung: We can get to a point where chiplets become a commodity, and a company can build millions of them because lots of customers want that small part. But not yet.
Q (Microchip): Is there a scenario where the substrates might become common, like some version of a breadboard?
Alphawave: I dream of that for the MPW for every shuttle. UCIe/BoW could help for MPW.
NIVIDA: Start with 2D.
And with that, the hour and twenty minutes had flown by.
As it happens, I have just the way for you to learn more. Along with some colleagues from Cadence, I wrote the book on chiplet-based design. It is called 3D-IC Trends: 2023 Outlook and is available on Amazon. I plan to be at DVCon and CadenceLIVE Silicon Valley giving copies away. So buy it now for $9.99 (or something close in your local currency), or show up at one of these events and track me down at the Cadence booth, probably during lunch. I'll sign your copy.
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