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A lot of aspects of EDA and semiconductor are fairly easy to predict: you read off the process roadmap for the big guys and work out the implications for tools, IP, and methodology. Of course, it is harder back away from the leading edge since that is not driven by technology: it is a lot less clear what are the business opportunities for, say, 90nm and whether there are aspects of leading-edge design tools that should be back-ported to 90nm. After all, despite the leading edge getting all the glory, a lot of designs are done at 28nm, 90nm, and even "older" technologies.
But the leading edge is driven by process technology. To be fair, process technology is driven by equipment technology, especially in the lithography area, and especially the implications of the introduction of EUV into volume manufacturing. To find out what is going on at the top of the funnel of process technology, I think the two top resources are following what imec is doing (since they look at everything and work with everyone), and attending IEDM, the International Electron Devices Meeting. The weird name is because it has been going on for 64 years, and back when it started an "electron device" was a vacuum tube (valve in UK), transistors were relegated to a little section on the last afternoon, and integrated circuits had still to be invented.
IEDM is December 1st to 5th at the Hilton Union Square in San Francisco (as it will be for the foreseeable future since they no longer alternate with Washington DC). The day-by-day format is the same as usual:
Slotted in at the last moment are a couple of "Late News Papers." These are traditionally from industry leaders revealing the first details about their next-generation processes. There are two this year, one from Samsung on their 3nm GAA (gate-all-around) logic process, and one from imec on continued scaling for DRAM. These are probably the biggest discontinuities in semiconductor leading edge, since the third key technology, flash, has already gone through its big transition to 3D.
On Saturday, there are 6 tutorials, given in three parallel sessions in morning and afternoon:
On Sunday there are two short courses given in parallel (so you can only attend one). Traditionally, one is logic-focused and one is memory-focused, and this year sticks to tradition. Despite being called "short", these courses actually last all day. This year they are:
Short Course 1: Scaling Survival Guide in the More than Moore Era
Short Course 2: It’s All About Memory, Not Logic!!!
Monday opens with the plenary session. This starts out with a welcome to IEDM and various awards, followed by three keynotes. This year the keynotes are:
During the remaining two and a half days there are specialist sessions on areas of device physics that you really have to be a researcher in the area to completely understand. Sprinkled through are focus sessions of a more general nature. I'll just give you the topics:
But there is more in a zillion other sessions, including Neural Networks, Memory Technology, Advanced CMOS, Photonics, and more.
Full details, including links for registration, are on the IEDM website.
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