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Yesterday, Cadence announced the Verisium AI-Driven Verification Platform. Underlying that is the Cadence Joint Enterprise Data and AI (JedAI) Platform that we also announced yesterday. But Breakfast Bytes only comes out once a day (only hobbits have second breakfast), so I'm covering that today.
Perhaps the biggest challenge in chip design today is that every design group is headcount constrained. Even if there is budget available, there are simply not enough designers. The only solution is to improve productivity by adding AI to design tools. But AI requires large amounts of data for training and every year the numbers only go up. Ad hoc approaches such as text files and spreadsheets have long since been outgrown by the volume and complexity of the data. The Cadence JedAI Platform delivers an open enterprise-grade, AI-driven, large-scale, cloud-enabled, data analytics environment, optimized for vast quantities of EDA data. EDA data covers a wide range of heterogeneous, structured and unstructured information which is not easy to store and process in general-purpose environments. The Cadence JedAI Platform is a cross-Cadence big data analytics solution that has been built from the ground up to support EDA-type data, such as design data, RTL, netlist, waveforms, workflow data, tools, and methodology. Also workload data such as runtime, memory usage, disk space usage, and so on. The Cadence JedAI Platform also provides comprehensive application programming interfaces (APIs) and industry-standard scripting tools, such as Python, Jupyter Notebook, REST APIs, enabling AI-driven, big data analytic applications (apps) to be created by the user, allowing engineering teams to visualize data and trends, and automatically generating practical design improvement strategies.
By using the Cadence JedAI Platform, designers can quickly identify trends and optimization to achieve the critical power, performance, and area (PPA) objectives while reducing design bottlenecks, resulting in faster design closure with fewer engineering resources.
The Cadence JedAI Platform enables a generational shift from single-run, single-engine algorithms in electronic design automation, to algorithms that leverage big data and AI to optimize multiple runs of multiple engines across an entire SoC design and verification flow.
A great example of how Cadence JedAI Platform is being used is the Verisium AI-Driven Verification Platform that we announced yesterday.
The Verisium platform is built on the Cadence JedAI Platform, natively integrating the Cadence Xcelium, Jasper, and Palladium verification engines. Using the Verisium platform, all verification data, including waveforms, coverage reports, and log files, are brought together in the Cadence JedAI Platform. Machine learning models are built and other proprietary metrics are mined from this data to enable a new class of tools that dramatically improve verification efficiency. The Verisium platform delivers a suite of apps such as AutoTriage, PinDown, WaveMiner, and Debug, leveraging big data and AI to optimize verification workloads, boost coverage and accelerate root cause analysis of bugs, improving overall verification productivity. By combining the Verisium platform and the Cadence JedAI Platform, a new era of AI-driven verification and debug has been enabled. For a deeper dive into Verisium AI-Driven Verification, see yesterday's post.
We announced Cadence Cerebrus Intelligent Chip Explorer a little over a year ago (see my post Cadence Cerebrus - Intelligent Chip Explorer for more details). Although we didn't announce it at the time, Cadence Cerebrus also runs on top of the Cadence JedAI Platform.
Cadence Cerebrus automates design optimization using reinforcement machine learning and scalable distributed computing, delivering improved PPA more quickly than a manual, iterative approach. To enable the reinforcement learning process, Cadence Cerebrus generates a lot of design metrics data and machine learning models, which the Cadence JedAI Platform can utilize in various ways. For example, based on historical Cadence Cerebrus ML model data, the Cadence JedAI Platform, using AI-driven analytics, can predict and generate a customized ML model for future designs, significantly reducing the run time for Cadence Cerebrus to generate an optimized design. These kinds of productivity benefits can only be achieved by integrating big data analytics into the design optimization process.
See the Cadence JedAI Platform product page.
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