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CadenceLIVE: Xilinx's Thunder-Bus

By Paul McLellan | 23 Aug 2021

At CadenceLIVE Americas in June, Raghukul presented on Thunder-Bus, a low-latency bridge between Xilinx FPGAs to accelerate system validation. Since Cadence's Protium X1 and X2 are also built using Xilinx FPGAs, Thunder-Bus can be used to co...

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protium x2 | Protium | xilinx
Rowhammer: Beating DRAM into Submission

By Paul McLellan | 20 Aug 2021

Way back in 2014, a DRAM vulnerability called Rowhammer was revealed. This is a silicon vulnerability. As the capacity of DRAMs has gone up, the size of the capacitor that holds each bit has shrunk, and as a result each bit is represented by fewer an...

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security | ddr5 | Memory | DDR4 | JEDEC | DRAM | rowhammer
Tensilica ConnX B10 in GF 22FDX for Automotive Grade 1

By Paul McLellan | 19 Aug 2021

At CadenceLIVE Americas back in June, GlobalFoundries presented a case study on using a Tensilica ConnX B10 DSP in their 22FDX process in a design that had to meet automotive grade 1 requirements. The study was to see what was the impact on power, pe...

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adaptive body bias | 22fdx | abb | gf | GlobalFoundries | FD-SOI
BlackHat: Hacking a Capsule Hotel—Ghost in the Bedrooms

By Paul McLellan | 18 Aug 2021

Security conferences always seem to have at least one interesting presentation that tells a fascinating story, albeit with a serious underlying security message. Here are three from the last few years (and this post is another one). RSAC: Motherhood...

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security | blackhat
Aerospace and Defense Day

By Paul McLellan | 17 Aug 2021

At the end of July, Cadence had its CadenceCONNECT Aerospace and Defense Day. For the rest of this post, I'm just going to say A&D for Aerospace and Defense. The focus of A&D Day was the same as a major focus of the Department of Defense ...

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A&D | RF | celsius | 3D-IC | awr | Analysis | thermal | aerospace & defense | Custom IC | clarity
Sunday Brunch Video for 8th August 2021

By Paul McLellan | 8 Aug 2021

https://youtu.be/_dRTQm0DyG0 Made in New York City (camera Carey Guo) Monday: Intel's Process and Packaging Roadmaps Tuesday: The Systems Designer's Guide to...Systems Analysis Wednesday: Offtopic: Today You, Tomorrow Me Thursday: V...

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sunday brunch
Offtopic: Today You, Tomorrow Me

By Paul McLellan | 4 Aug 2021

It is the last day before a break and so I write about whatever I feel like. It's not an official holiday, but I'm going to the East Coast to see my kids, who both live in New York and so I haven't seen them for nearly two years. I haven't seen my 93...

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offtopic
The Systems Designer's Guide to...Systems Analysis

By Paul McLellan | 3 Aug 2021

There is a new book in the System Designer's Guide to... series, published by i.007e books. The book is written by Cadence's Brad Griffin and is titled System Analysis: Electromagnetic Interference and Thermal Analysis of Electronic Systems. ...

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featured post | system analysis | electrical analysis | Thermal Analysis
Intel's Process and Packaging Roadmaps

By Paul McLellan | 2 Aug 2021

There are only three companies that are on the real leading edge. As you probably know, Intel has been struggling to keep anything close to its tick-tock cadence of process nodes, with problems at both 10nm and 7nm. On July 26, Pat Gelsinger, Intel's...

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Intel | intel 4 | featured post | intel 7 | emib | process roadmap | intel 3 | foveros | intel 20a
Sunday Brunch Video for 1st August 2021

By Paul McLellan | 1 Aug 2021

https://youtu.be/I0AYf5V_irg Made in Long Ridge Open Space Preserve (camera Carey Guo) Monday: HOT CHIPS 2021 Preview Tuesday: Designed with Cadence Video Series Wednesday: July Update Thursday: Offtopic: Immersive Vincent van Gogh Friday: Caden...

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sunday brunch
Offtopic: Immersive Vincent van Gogh

By Paul McLellan | 29 Jul 2021

Cadence has a global holiday tomorrow and Breakfast Bytes will not appear. Back on Monday. Did you see the (excellent) Netflix show Emily in Paris? In one episode, the characters go to see a show which is called Immersive van Gogh. In Paris, it opene...

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offtopic | van gogh | immersive van gogh
July Update

By Paul McLellan | 28 Jul 2021

This is the July edition of the now monthly update post, with small updates to existing posts and themes that don't justify a whole Breakfast Bytes post on their own. Cadence is off for a global recharge day on Friday, so Breakfast Bytes will not...

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ransomware | featured post | 6ghz | update | inmos | spectrum | GlobalFoundries | supply chain attack | newport wafer fab
Designed with Cadence Video Series

By Paul McLellan | 27 Jul 2021

Designed with Cadence is a video series made with Cadence customers about how they used Cadence technology to design real products. Each video is about two to three minutes long. There are currently more than 20 of them, with new ones being added eve...

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featured post | video | designed with cadence | dwc
HOT CHIPS 2021 Preview

By Paul McLellan | 26 Jul 2021

As usual in August, it is HOT CHIPS. I always find this one of the most interesting conferences of the year. It gives a lot of insight into the specific products being presented, but also a feel for what technologies are being used for the most advan...

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Intel | AMD | IBM | Samsung | hot chips | ARM
Sunday Brunch Video for 25th July 2021

By Paul McLellan | 25 Jul 2021

https://youtu.be/cwT7KL4iShY Made on "a tropical beach" Monday: Aerospace and Defense Systems Day...and DAU Tuesday: 75 Years of the Microprocessor Wednesday: CadenceLIVE Cloud Panel Thursday: Cerebrus: The Future of Intelligent Chip D...

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sunday brunch
Machine Learning in EDA

By Paul McLellan | 23 Jul 2021

Yesterday, in my post Cerebrus: The Future of Intelligent Chip Design , I talked about our latest product to use machine learning (ML) techniques to great effect. Although they are all slightly different, machine learning is also known as artificial i...

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featured post | xcelium ml | cerebrus | JasperGold | allegro x
Cerebrus: The Future of Intelligent Chip Design

By Paul McLellan | 22 Jul 2021

This morning, Cadence announced Cerebrus Intelligent Chip Explorer, a machine learning (ML)-based tool that automates and scales digital chip design. If you think about what a designer does with traditional EDA tools, a lot of it is running some tool...

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Genus | featured post | cerebrus | cloud | cadence cloud | Innovus | digital full flow | physical design | Synthesis | timing signoff
CadenceLIVE Cloud Panel

By Paul McLellan | 21 Jul 2021

At the recent CadenceLIVE Americas, most of the sessions were pre-recorded with a live Q&A at the end. One exception to this was Big 3D FEM Simulations: Cloud or On-Prem? FEM stands for "finite element method" and is part of the te...

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featured post | on-prem | cloud | cadencelive americas | cadence cloud | cadencelive
75 Years of the Microprocessor

By Paul McLellan | 20 Jul 2021

At the recent ISCA, there was a panel session with some of the major contributors to microprocessor development during the last 50 years. They were also asked to predict how they thought the microprocessor would develop during the next 25 years, goin...

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isca | microprocessor
Aerospace and Defense Systems Day...and DAU

By Paul McLellan | 19 Jul 2021

Coming up on July 28 is CadenceCONNECT Aerospace and Defense Systems Day. Cadence experts will present on the most important issues facing teams in aerospace and defense (A&D). There is a common thread running through the presentations, namely ho...

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A&D | featured post | Aerospace | eda101 | cadenceconnect | defense | dau
Sunday Brunch Video for 18th July 2021

By Paul McLellan | 18 Jul 2021

https://youtu.be/nZ4lisR19nQ Made on my balcony (camera Carey Guo) Monday: Tesla Goes All-In on Vision...and Supercomputers Tuesday: 50 Years of the Microprocessor, Part 1 Wednesday: 50 Years of the Microprocessor, Part 2 Thursday: AWR: Int...

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sunday brunch
What Comes after 2nm GAA?

By Paul McLellan | 16 Jul 2021

There are three companies that currently pursue the smallest geometries, what I've heard called "the race to the end of Moore's Law". One is based in Korea, one in Taiwan, and one in the US. So the obvious place to go to find out wh...

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forksheet | 3nm | imec | airgap | 2nm
AWR: Intelligent RF Design

By Paul McLellan | 15 Jul 2021

There is a new release of the AWR Design Environment with cross-platform workflows to support RF to mmWave based on both the Virtuoso (chip) and Allegro (PCB/package) platforms, and with integration to the system-level analysis solution Clarity ...

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5G | RF | featured post | awr | RF design | awr v16 | radios
50 Years of the Microprocessor, Part 2

By Paul McLellan | 14 Jul 2021

At the recent International Symposium on Computer Architecture (ISCA) there was a special session to celebrate the 50th anniversary of the microprocessor, with eight experts who had influence during those decades. The introductory statements from the...

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isca | microprocessor
50 Years of the Microprocessor, Part 1

By Paul McLellan | 13 Jul 2021

At the recent International Symposium on Computer Architecture (ISCA) there was a special session to celebrate the 50th anniversary of the microprocessor, with eight experts who had influence during those decades. They were: Federico Faggin, design...

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isca | moore's law | microprocessor

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