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I have found that the combination of Virtuoso's placer and router is very powerful for implementing smaller digital standard cell blocks. The placer can be used to create rows and then place the standard cells within the rows along with filler cells, much like a Big-Digital P&R placement tool. After placement, the router can be used to route the digital block. I have developed a demo that shows how Cadence's placement and routing technology can be used to quickly place and route a small digital block that has about 200 standard cells within just a few minutes. I have been showing this flow to several customers in Asia and North America and the feedback has been very positive.
The setup required for such a flow is straight forward. Assuming you already have a complete technology file with all required spacing rules for the technology node you are working on, there are only a few other things to make sure are setup:
Component Types (Std Cell component type must be defined for your standard cells and filler cells)
VirtuosoDefaultSetup constraint group must have the proper valid router layers and vias defined for routing
After that, you can use the Placement Planning utility to create the power rails and rows that will be used to place your standard cells in. After the rows are created, you can used the Auto Placement GUI to run the custom digital placer. For my block with 5 rows and 200 standard cells, the placer ran in just under a minute. It is quite impressive to see how fast the placer runs. After placement, you can use the router to route the design. For this design, the router ran in about 5 minutes. I had a completely placed androuted digital block in under 10 minutes.
If you need to quickly place and route a small digital block, it would be worthwhile to look at Virtuoso's Custom Placer and Space-Based Router in IC6.1.3 to place and route the block.
Hi John, I'd like to download the training material for this workshop. Could you please send me the workshop material? Thanks
Yes, you can do a similar flow in IC5141 using VCP and VCAR, although the IC5141 flow is less integrated than in IC613. That is, in the IC5141 flow, you will need to launch the router (VCAR) as a seperate tool outside of virtuoso (different GUI). Where in the IC613 flow described above, you can perform the routing from the Virtuoso Layout GUI. Please also note that for 65nm (and smaller), you will need to use VSR as VCAR does not support 65nm (and smaller) rules. Hence, if you try to route a 65nm, or 45nm design with VCAR, you will be left with many DRC errors, where VSR does support 65nm (and smaller) rules.
I have a workshop available that goes over this flow. If your are interested, please send me an email: email@example.com.
Is such feature only available in IC6.1.3 platform ? I have used the VCAR/CCAR in IC5141 platform to do the similar things, but i don't know what are the improvements this tool provides in IC6.1.3
Would you also share your demo to me after you complete the demo script ?
Thanks. Mike Yi
Yes, that is true. The place and route flow within does not take timing into account.
So this flow would be great for customers that need to implement small digital blocks without timing. I need to write up the demo script before I distribute the demo. I will do that shortly and let you know when it is ready. Thanks for your interest.
The demo and flow you have suggested would be very helpful for customers who do not care about timing and has a small digital block to place and route...Thanks for sharing. Do you have the demo available so we can download it and get a better understanding of the tool. Best Regards,Mariam