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An increasing number of mixed-signal design teams are contemplating adding analog behavioral modeling to their repertoire in order to achieve reasonable simulation speeds. Utilizing analog behavioral models can yield simulation performance improvements that can make full chip verification a reality. This approach can be several magnitudes faster than transistor-level; however, the actual performance improvement is greatly dependent on the level of detail in the model, as well as, the language of choice. Analog behavioral models are generally written in one of the languages below:
Verilog-AMS – A derivative of Verilog, it includes analog and mixed-signal extensions in order to define the behavior of analog and mixed-signal systems, providing both continuous-time and event-driven modeling Wreal – An extension of the Verilog-AMS modeling language allowing analog block operation as a real data flow model Verilog-A – An extension of Verilog to describe analog and non-electrical behavior as a continuous-time subset VHDL-AMS (IEEE1076.1) – similar in concept to Verilog-AMS, providing analog and mixed-signal extensions in order to define the behavior of analog and mixed-signal systems
Verilog-AMS – A derivative of Verilog, it includes analog and mixed-signal extensions in order to define the behavior of analog and mixed-signal systems, providing both continuous-time and event-driven modeling
Wreal – An extension of the Verilog-AMS modeling language allowing analog block operation as a real data flow model
Verilog-A – An extension of Verilog to describe analog and non-electrical behavior as a continuous-time subset
VHDL-AMS (IEEE1076.1) – similar in concept to Verilog-AMS, providing analog and mixed-signal extensions in order to define the behavior of analog and mixed-signal systems
One of the biggest challenges in the creation of analog behavioral models is; whose job is it? The analog designer is the most familiar with the circuit performance and specific behaviors, however, many analog designers typically are not programmers and familiar with the languages mentioned above. The digital designer, who also tends to be the full chip verification engineer, is most familiar with programming languages, but lacks the analog specific circuit knowledge. Therefore, a blend of both skill sets is required or a conscience effort for both designers to work together. One must continually make the tradeoff of effort versus benefit when deciding to create an analog behavioral model. Some of the questions that come to mind are: Can I re-use it? How long will it take me to create a high quality model? What performance gains can I expect?
Finally, as you consider adding analog behavioral modeling to your design repertoire; consider your modeling goals and language. A performance model needs to capture specific circuit behavior and can affect your effort versus benefit equation, while a functional model requires you to only capture the 1st order effects that are needed to verify the circuit functionality. Model On!
And what about SystemC-AMS ?
I agree analog designers are not so at ease with programming, but SystemC-AMS is to be mentionned in the list.
I feel both functional ( basic ) and performance modeling is critical at different phases of a project. In the beginning phase when both analog and digital designs are still under construction, a basic functional model can catch a lot of simple issues like connectivity, bit-swapping and polarity issues which can then be immediately rectified. Once design is a bit stable, model can be improved towards performance side so that other complicated issues can then be caught with faster simulations.
As u rightly put, digital designers have littel knowledge and analog designers are not familiar with modelling nor do they have time in most cases. Also, there is a lot of communication gap between analog and digital designers mostly due to totally different skill set needed for both. Its best to have a dedicated AMS verification engineer who knows both digital and analog basics and is also good in modelling. It can relly help bridge the gap and help catch a lot of issues much earlier in the design phase speeding up the tape out process dramatically.