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An increasing number of analog and mixed-signal designs in automotive, power management, wireless, medical, and industrial applications require digital control. But designing a state machine, and integrating the increasing amount of logic gates that implements it, has been challenging for analog designers. They often start implementing some digital functionality using a custom methodology, but soon the growing gate count becomes overwhelming and requires digital skills.
Analog designers then find they need a more complete digital flow for the digital block design. This flow must work smoothly in conjunction with an analog-centric flow for top-level design and full-chip integration. The increasing size of digital logic requires formal verification, test insertion, and automation for low power techniques. The amount of digital logic might increase to the point that a digital-centric methodology is more suitable for full-chip integration, with analog functionality designed separately and integrated as black boxes.
Integrating a core processor within analog and mixed-signal designs is an attractive alternative for digital control. The processor architecture offers a high level of flexibility through programmability and scalability, thus realizing more advanced designs and meeting more complex specs. The benefits outweigh an initial investment in architectural development and a design methodology shift.
Cortex-M0 Targets Mixed-Signal Applications
ARM recently released the Cortex-M0 processor core targeting mixed-signal applications. It has a 32-bit architecture, compact instruction set, very small silicon footprint (base configuration is just about 12K gates) and is power efficient. In a typical application it is accompanied by a memory block, memory bus interface, peripheral interfaces (GPIO, I2C, UART, SPI, USB) and standard analog/mixed-signal IP (PLL, ADC, DAC). As such it is suitable for integration within analog sensors, RF transceivers, power regulators, LED drivers, barcode scanners, motor controllers, or similar applications.
At the end of last month, ARM organized a Cortex-M0 workshop in Paris, France, and invited Cadence to present design solutions. Judging by number of attendees and their strong interest, the future of analog and mixed-signal design lies in its integration with processor cores. Almost thirty companies from the region came to learn how to design mixed-signal applications with the Cortex-M0 processor core.
The Cadence mixed-signal solution spans different design styles and supports diverse applications while leveraging common technologies. For example, verification of the mixed-signal designs with embedded Cortex-M0 core can be done from either the schematic driven Virtuoso-ADE environment or the command-driven Incisive environment. Both use the same high performance, tightly integrated simulation engines including those for SPICE, RF, behavioral, RTL and gate-level simulation. This ensures consistency of results while analog and digital designers work in their preferred use models.
Similarly, physical implementation and signoff for analog-centric designs is done in Virtuoso for the high level of control required in crafting analog circuits, with a seamless integration to the Encounter Digital Implementation System for digital block implementation. If a design requires a digital-centric environment, Encounter offers the full strength of digital design automation and low power design techniques, with the ability to integrate analog blocks previously done in Virtuoso as hard macros. Both analog and digital centric design environments leverage Virtuoso-Encounter interoperability based on industry standard OpenAccess (OA) for sharing design data and constraints. The implementation solution extends to IC/package co-design through Virtuoso and an interoperable flow with the Allegro package and board design environment.
Bringing Digital Capabilities to Analog Designers
Many analog/mixed-signal design teams are facing the need for digital design capabilities for the first time. They might be intimidated by complexity and price of digital design tools they need to apply for a relatively small logic gate count, as compared to mainstream digital. Cadence has conveniently packaged digital capabilities for Virtuoso users who need a digital solution for limited-size digital block implementation.
The Virtuoso Digital Implementation package contains logic synthesis, placement, clock tree synthesis, timing optimization, routing, extraction and static timing analysis. This is the same Encounter technology but is limited to 50K instances, sufficient for most mixed-signal designs with Cortex-M0. Moreover, two Virtuoso Digital Implementation licenses can be combined to double the capacity, and there's a smooth path to the full Encounter configuration if digital design needs increase.
In addition to flows, Cadence offers highly experienced mixed-signal methodology and design services, and a complete ecosystem from IP providers to foundries.
With Cortex-M0, ARM has offered a simple but powerful processor core for mixed-signal applications. The Cadence mixed-signal solution enables designers to smoothly realize designs in silicon, with high design productivity, schedule predictability and project profitability. Offerings from both companies lower the barrier for adoption of processor cores in analog and mixed-signal applications, and I believe many designers will take advantage of them.
Note: The ARM workshop in Paris was first in serious of similar workshops. The next one is planned for middle of July in Zurich. Please contact your local ARM or Cadence representative for this or possible future workshop in your region.