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In my last blog, Virtuoso IC 5.1.41 was Good but Virtuoso IC6.1 is Better, I wrote about the improvements in Open Access, SKILL and Virtuoso Schematic Editor in Virtuoso IC 6.1. In this blog, I am going to focus on Virtuoso Analog Design Environment, mainly on Virtuoso Analog Design Environment XL, its design analysis and verification capabilities, and how design teams can take advantage of these features to increase productivity.
The Virtuoso Analog Design Environment offers comprehensive set of capabilities required to fully explore, analyze, and verify a design against the design's specifications. The tiered product structure of the Virtuoso Analog Design Environment provides designers with the flexibility to select the tier that meets their design needs, enabling efficient use of EDA tools.
Virtuoso Analog Design Environment L
Virtuoso Analog Design Environment L provides a quick entry into the analysis process with easy execution of simulations. Virtuoso IC 6.1 Analog Design Environment L provides users with a short learning curve and easy transition from previous versions of Virtuoso. Apart from maintaining the same use model, Virtuoso Analog Design Environment L has many new features to enable efficient design analysis and simulation, including:
To know more about Virtuoso Analog Design Environment L, click here
Virtuoso Analog Design Environment XL
Virtuoso Analog Design Environment XL is an advanced tier that extends the L tier capabilities, providing a multiple test bench environment; analysis over sweeps, corners, and Monte Carlo analysis; and easy reviewing of results and generation of spec comparison sheets and datasheets as needed.
One of the important features of Virtuoso Analog Design Environment XL is its multi-test bench environment. Historically, custom/analog designers are used to setting up one test bench at a time, run simulation(s), analyze results, improve the design to meet design specifications, and then move on to the next test bench or next stage of the design. This methodology was necessitated not only because of hardware limitations but also because of limitations of available EDA tools.
However, with powerful hardware resources now being made available to designers, analyzing one test bench at a time not only is inefficient but also limits the designer's ability to simultaneously analyze different design architectures and test benches, and quickly settle on designs that meet the requirements. Virtuoso Analog Design Environment XL was designed and developed to overcome this shortcoming in existing tools.
The multi-test bench environment of Virtuoso Analog Design Environment XL allows designers to simultaneously run multiple test benches and efficiently analyze design specification compliance. Designers can analyze multiple test benches of the same design (with a different setup) or multiple test benches on different designs, using the same setup to enable optimum use of design infrastructure.
Some of our major customers who have adopted Virtuoso Analog Design Environment XL in their design flow are making use of this methodology to comprehensively analyze vast design spaces by running hundreds of simulations on multiple test benches, and by farming out these simulations onto larges farm of hardware resources. During a recent customer visit, I found out that designers are taking advantage of the "test specific job policy" to quickly get to the results of the simulations they are interested in while other simulations are still going on. Making use of a test specific job policy in conjunction with the multi-test bench environment is a clever way of using different hardware farms that are available to designers.
Designers can sweep design variables across multiple test benches to perform extensive design analysis and verification. The ability to enable/disable sweeps for each test gives designers the flexibility to customize analysis and verification plans to meet design requirements. An easy to use design debug environment allows designers to quickly access the required information of failed simulations, allowing designers to analyze issues that are causing design performance issues.
Apart from sweeps, designers can also perform corners analysis and Monte Carlo simulations across these test benches in the same setup. I will be covering these topics in my upcoming blog. Finally, designers can make use of Analog Design Environment XL setup for pre and post-layout simulations to analyze layout parasitic effects
In summary, whereas Virtuoso Analog Design Environment L provides designers with the same use model as the one designers are used to with previous versions of Virtuoso ADE (such as analyzing one test bench at a time), Virtuoso Analog Design Environment XL provides designers with the powerful multi-test bench environment, resulting in increased designer productivity, the efficient use of design infrastructure, and comprehensive design analysis and verification.
To get more details about Virtuoso Analog Design Environment XL and find out how design teams can adopt Virtuoso Analog Design Environment XL in their design flow to take advantage of the productivity enhancing features mentioned in this blog, please contact your Cadence Application Engineer.
Here are the links to some of the Virtuoso Analog Design Environment XL videos.
Note: You need a COS (Cadence Online Support) account to access these videos.
Creating new Analog Design Environment XL view from Analog Design Environment L and Opening existing Analog Design Environment XL view in Analog Design Environment L
Setting up multiple tests in Virtuoso Analog Design Environment XL
Setting specifications & running simulations in Virtuoso Analog Design Environment XL
Variable & parameter sweeps in Virtuoso Analog Design Environment XL
Virtuoso Analog Design Environment XL Debug Environment