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In my last blog, Virtuoso Analog Design Environment XL - Embrace the Productivity, I wrote about Virtuoso Analog Design Environment XL's multi-test bench environment and how design teams can make use of this feature to increase productivity and use hardware resources efficiently. In this blog, I will focus on advanced Virtuoso Analog Design Environment XL features like corners analysis and Monte Carlo analysis.
Decreasing geometries, along with increasing design complexity in an era of short time-to-market windows, are making the task of designing custom analog ICs very difficult. Add to this the task of designing and verifying designs for a large number of PVT (Process, Voltage & Temperature) corners, and it is easy to understand the designer's need for efficient tools that make their lives easier. Corners analysis in Virtuoso Analog Design Environment XL is one such capability that enablez designers overcome such challenges.
Using the new and improved corners analysis tool available in the Virtuoso Analog Design Environment XL, designers can perform comprehensive analysis and verification across multiple corners to ensure design specification compliance. Apart from predefined PVT corners, designers can also create corners on various design parameters to increase the design space coverage and to ensure that their design meets the performance requirements over a wide range of operating conditions. A color coded display of spec-compliant corners analysis results in Virtuoso Analog Design Environment XL, combined with an easy to use debug mechanism, makes it easy for the designer to quickly get to the results they are interested in and to identify underlying issues that might be causing design spec violations. Virtuoso Analog Design Environment XL provides designers with the ability to run just the failed corner cases with a single click of a button and quickly identify problem areas.
Note: In Virtuoso 6.1.5, as part of "Worst Case Corners" tool, users can take advantage of efficient algorithms to create worst case corners and reduce the number of corners to simulate from 100s to single digits. "Worst Case Corners" is a Virtuoso Analog Design Environment GXL feature and you can find out more about worst case corners and other Virtuoso Analog Design Environment GXL features here.
Monte Carlo Analysis
Just as corners analysis is needed to verify design performance across PVT corners, Monte Carlo analysis is becoming critical for designers to better understand design performance with respect to statistical variations. Monte Carlo analysis in Virtuoso Analog Design Environment XL allows designers to analyze deign performance against statistical variations and take corrective actions where needed to increase the yield. Designers can selectively enable/disable Monte Carlo analysis on a complete design, or just parts of it, to study the effects of statistical variation.
The in-memory integration of Virtuoso Analog Design Environment XL's Monte Carlo analysis with Cadence MMSIM tools provides faster and efficient simulations by removing the overhead encountered with Monte Carlo tools offered by 3rd party vendors. Apart from a close integration with MMSIM tools, Virtuoso Analog Design Environment XL's Monte Carlo analysis also provides advanced algorithms to effectively reduce number of trials needed to cover the entire design space. The ability to plot histograms and scatter plots in Virtuoso Visualization & Analysis (ViVA), Cadence's latest waveform display tool, combined with the Virtuoso Analog Design Environment XL's debug environment (users can open a Virtuoso Analog Design Environment L session on failed simulations with all the variable settings used in that particular Monte Carlo trial), allows designers to analyze results and help identify underlying reasons for failed simulations.
Note: It is a well known fact that regular Monte Carlo analysis is very expensive (in terms of number of simulations needed) to predict high-sigma yield. In such cases, you can use High-Sigma yield analysis. High-Sigma analysis enables designers to predict yield up to 6 sigma, i.e. 3.4 ppm failures with fewest possible number simulations. This is a Virtuoso Analog Design Environment GXL feature and you can find out more about High-Sigma yield analysis and other Virtuoso Analog Design Environment GXL features here.
Here are the links to some of the Virtuoso Analog Design Environment XL videos. Note: You need a COS (Cadence Online Support) account to access these videos.
Setting up & Simulating Corners in Virtuoso Analog Design Environment XL
Using the New Corners Setup Form in Virtuoso Analog Design Environment XL (IC 6.1.5)
Incremental Resimulation in Virtuoso Analog Design Environment XL
Debugging Points of Simulation Results in Virtuoso Analog Design Environment XL
Monte Carlo Analysis in Virtuoso Analog Design Environment XL