Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Although many automatic layout generation tools are available to automate design creation, the layout modification/correction step (fixing design rule violations) is not automated very well. Consequently, design modification including error correction typically needs to be done manually. A good solution to automate the layout modification/correction step can be provided by a layout optimization tool that optimizes the areas containing design rule violations in a layout, and fixes the violations automatically. Such a capability is provided by the Interactive Design violation Fixing (IDF) tool that was first provided in the Virtuoso IC6.1.4 release.
The primary advantages of IDF are:
1. Only required areas are modified and corrected (nothing will be changed outside of the selected areas.)
2. It can be called any time in any design phase (even if the layout has not been finalized.)
3. Quality of the modified layout is stable (the results won't vary according to engineers' experience or design manner.)
As the first step to realize the above requirements, IDF was implemented in our IC6.1.4 software release by freezing (not changing) details outside of specified areas. (Fig 1)
Fig 1. IDF- IC6.1.4 (freeze outside of the area to be optimized)
Although the IDF in IC6.1.4 worked very well, freezing areas around the area to be optimized had the following two limitations:
1. It takes long time when a design is big because the entire layout data needs to be loaded on the dynamic memory.
2. When multiple areas are selected, one optimization failure ("infeasible") causes the optimization failure of all selected areas. (All areas must be optimized at the same time since optimizing a design means generating a result that satisfies all requirements simultaneously.)
Therefore, IDF needed to be enhanced so that automated layout modification/correction worked regardless of the design size, and without infeasible results interrupting the flow. In the latest release, IC6.1.5, the IDF has successfully been enhanced to realize the above requirements.The solution to the problem is applying the automated correction (IDF) only to the affected region. The areas to be optimized from a design are extracted. Then, the extracted areas are sent to the IDF engine one by one (Fig. 2)
Fig 2. IDF in IC6.1.5
IDF works very fast in most cases because the size of the data is very small. The following table compares benchmark results of IDF in IC6.1.4 and in IC6.1.5. IDF in IC6.1.5 finishes all error fixing within 1 minute.
Table 1. Runtime comparison (Frozen Donut Area vs. Area Segmenting Method)
*1) Job was terminated during constraint generation phase.*2) 2 Infeasible results were reported.
Runtime (User time) was measured. Test Machine: VMWare Virtual Machine Redhat Linux 4RAM: 1 GB
Physical Machine:Dell Laptop PC M65CPU :Intel Core 2 CPU 2.16GHz RAM : 3.25 GBOS Windows XP SP3
Figure 3 shows the biggest design used for this benchmark test.
Fig. 3 Analog PLL design 650um X 550um（# of DRC Errors 30 -> 2 : runtime = 30sec)
This approach (loading only the specified area) allows the following benefits:
IDF in IC6.1.5 works effectively for medium / large designs. It can also handle designs of chip-level complexity. Because each optimization task is discrete, the flow does not become interrupted by an infeasible result error. Also, the runtime is very fast, since the size of each extracted cell tends to be small.
Actually, IDF in IC6.1.5 consists of multiple small IDF fixes in IC6.1.4. Because a huge amount of design time is wasted on inefficient manual modifications, IDF in IC6.1.5 is a great solution to correct errors. IDF in IC6.1.5 is the answer to industry’s demand for automatic error correction.
Sr. Engineering Manager, Physical DesignSan Jose R&D, Custom IC, Silicon Realization Group
This article is very attractive and interesting. can you explain "IDF needed to be enhanced of the design size, and without infeasible results interrupting the flow."
IDF requires 8 GXL tokens.
Because it runs on XL / GXL, additionally, the Virtuoso XL license, or 4 tokens or Virtuoso GXL is needed.
Which licenses are needed for this feature?
IDF can be used from GXL or XL.
So, in GXL, or XL environment,
“Interactive DRC Fixing” will appear one of the items in the “Optimize” menu.
To active XL, or GXL,
Select Launch > Layout GXL (or Layout XL) from the menu bar on a layout window.
this feature looks very interesting. How do I start the Interactive Design violation Fixing (IDF) in Virtuoso. In the Optimize menu I do not see any menu item with that name.