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Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
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Topics in March include advanced analysis in ADE GXL, taking advantage of lots of features for doing statistical analysis in ADE XL, defining bindkeys in ADE L (yes, you can do that!), plus a variety of useful details in the areas of routing and advanced custom layout.
1. Design Tuning with Analog Design Environment GXL: Interactive and Automated Flows
Walks through a detailed example using several different advanced analysis tools, including Sensitivity Analysis, Manual Tuning, and Optimization. Includes demo database.
2. Statistical Analysis Quick Start (ADE XL)
Overview and quick reference covering the statistical analysis features in ADE XL, including setup options for Monte Carlo Sampling, defining confidence levels, using auto-stop, post-processing data using histograms, quantile plots and waveforms, and creating statistical corners.
3. Mixed-Signal PSL Assertions in AMS Designer
Provides an overview of writing mixed-signal PSL assertions to handle Verilog-AMS, analog values, etc. Includes a detailed case study, accompanying example tarkit and exercises.
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4. Power, Ground and Structured Routing Implementation Flow
The flow leverages a combination of existing Virtuoso functionality, Virtuoso Routing TCL commands, and custom SKILL scripts to enable users to efficiently build custom power, ground, and structured signal routes. The flow also supports creation of power and ground rough-in during early floorplanning. This flow is intended for analog mixed-signal designs at the chip, block, and device level in Virtuoso. Includes demo database and detailed documentation providing an overview of the flow, guidelines for use in your designs and step-by-step walkthrough using the demo database.
5. Mark Nets
This video describes the Mark Net command including Mark, Save, Unmark, Options, and Retaining Via Info.
6. Generating Clones in Virtuoso
This is a demo that describes generating clones in Virtuoso. It includes topics such as creating clones as Free Objects, Group Objects, and Synchronized Family.
7. VLS-XL: Modgen: Abutting Modgen members using SKILL (Solution 20033396)
Skill routine to use to abut all the devices in a given Modgen.
8. How to query directional spacing tables from techfile with SKILL? (Solution 20034969)
Some example Skill commands showing you how to access horizontal and vertical spacing rules from the techfile.
9. How to change nport file names for corner simulation (Solution 20040165)
You have an nport with an S-parameter file. For each corner, the nport uses a different S-parameter file. This solution shows you how to wrap up the nport as a subcircuit library with sections you can reference just like any other model file sections.
10. How to define bindkeys for ADE L window (Solution 20051691)
Shows you how to register bindkeys which will be active in the ADE L window. Examples provided to create bindkeys for "Netlist and Run" and Direct Plot commands.