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Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
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Feeling a bit lazy this month, but even without digging too deeply, I could find 16 new and interesting bits of content...
1. Adding and Managing CDF Parameters for Fluid Guard Rings (ICADV12.1)
Shows you how to add and update the Component Description Format (CDF) parameters and attributes that affect the geometry of a fluid guard ring (FGR) instance.
2. Customizing Create Guard Ring Form (ICADV12.1 ISR3)
How to use triggers and SKILL APIs to customize the Create Guard Ring form, change the properties of the pre-defined fields or components and create new components to suit your design requirements.
3. Virtuoso Schematic Editor Shortcuts for Improved Productivity
Guaranteed that you will learn some new tricks by reading through this document! Includes lots of tips on using wire labels, arrays of instances, the new Probes Assistant, customizing the UI and using bindkeys
Rapid Adoption Kits (RAKs)
4. Schematic Model Generator
Schematic Model Generator (SMG) is an easy-to-use GUI-based tool which allows users to create a reusable building block schematic, which is processes to create a textual behavioral model for a circuit. The RAK includes an overview presentation, documented tutorial with database and video demonstrations.
5. amsDmv - AMS Design and Model Validation
AmsDmv is a tool to validate similarity in measured results, simulated behavior and interfaces of a given reference (design) and compared (model) blocks, targeted primarily for analog/mixed signal models. The RAK includes a documented tutorial with database and video demonstration.
You can learn more about both of the above tools--amsDmv and Schematic Model Generator--in the archived webinar: Analog Behavioral Modeling and Model Generation.
6. Analog-on-Top Mixed Signal Implementation: Virtuoso Black Box flow with IC61
Introduces the Virtuoso Black Box Floorplan using Virtuoso Floorplanner (VFP). Includes documented tutorial and database.
7. Mixed Signal Simulation with Real Number Modeling
Learn the basics of invoking mixed signal verification and using real number modeling in both the Virtuoso GUI-based (AVUM) and Text-based command line (AIUM) flows. Includes overview presentation, documented tutorial with database and video demonstrations.
8. Mixed Signal Verification - Connectivity
Learn how connectivity is handled at the interface of logical, electrical and RNM (real number modeling) nets, what coercion is and how it benefits mixed signal verification, and what an IE (interface element) card is and how it can be used to customize mixed signal connectivity. Includes overview document and documented tutorial with database.
9. Static and Dynamic Checks
Describes the usage of the Spectre APS/XPS static and dynamic design checks available in MMSIM 12.1 ISR12. These checks may be used to identify typical design problems including high impedance nodes, DC leakage paths, extreme rise and fall times, excessive device currents, setup and hold timing errors, voltage domain issues or connectivity problems. RAK includes documented tutorial with database.
10. Mark Net - IC6.1.6 Enhancement
11. Rectangle Wire Reshape in IC 6.1.6
12. New features in SimVision 13.1 Release
13. VCDL (Virtuoso Connnectivity-Driven Layout)-Device Correspondence to Make Layout Connectivity Driven
14. Defining Common Centroid Constraint
15. Autorouting the Design using Virtuoso Shape-based Router
16. Use VSR (Virtuoso Shape-based Router) Features for Analog Routing