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Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
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Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
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This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
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Our folks over in Physical Design have been busy churning out helpful Rapid Adoption Kits to demystify lots of useful features in the Virtuoso Layout Suite. It's a great opportunity to learn some new productivity-boosting tricks.
1. Virtuoso Spectre Transient Noise Analysis
This document discusses the theoretical background of Spectre's transient noise analysis, its implementation and implications, and the latest use model together with many useful time-saving and circuit diagnostic features. It also provides several detailed tutorial examples.
Rapid Adoption Kits
2. IC 6.1.6 Rapid Analog Prototyping (RAP) Workshop
This is a front-to-back flow that uses the Virtuoso Constraint System to generate the layout of an analog circuit in an automated manner, in order to obtain early feedback on parasitics and device effects on circuit simulation. Includes an overview presentation, documented tutorial and database.
3. Virtuoso Parameterized Layout Generators (VPLGen)
VPLGen is a new feature that lets you easily generate and reuse layouts for schematic instances which differ by inherited parameter values so that the layouts can be used repeatedly throughout the hierarchy and reused across design libraries. VPLGen is a Cadence-supported hierarchical pcell that does not require coding. This RAK includes a documented tutorial and database, as well as a video demonstration.
4. VXL Back Annotation
This workshop walks you through an example of how to create a dummy using VXL and then how to back-annotate it into a schematic. It includes a documented tutorial and database.
5. Update Binding
This workshop is an example of how to take a layout that was created in a non-connectivity environment and make it VXL compliant. It walks through how using the new Update Binding command to simplify the task. Includes a documented tutorial and database.
6. Introduction to Connectivity-Driven Design in VLS XL
The move from Layout L to Layout XL is becoming increasingly important. The Layout XL environment contains functionality for the implementation of advanced-node designs, such as wire editing, connectivity- and constraint-driven layouts, mosaics, modgens, and electrically aware design. This Rapid Adoption Kit (RAK) will introduce how productivity can be increased by moving from Virtuoso Layout Suite L to Virtuoso Layout Suite XL. It includes a documented tutorial and database.
7. QuickView Introduction
QuickView is the Cadence stand-alone data viewing tool. It allows you to draw, examine, compare and validate integrated circuit (IC) data in various layout and pattern data formats. Includes documented tutorial and database.
8. IC6.1.6 Pin to Trunk Device-Level Routing
This material steps through the Pin to Trunk Device-Level Routing Flow in Virtuoso in IC 6.1.6. The objective of this flow is to increase layout productivity through improved routing functionality aimed at device-level interconnects. This flow enables users to quickly connect device pins in a structured topology. Includes documented tutorial and database.
9. IC6.1.6 Pin to Trunk Block-Level Routing
This material steps through the Pin to Trunk Block-Level Routing Flow in Virtuoso in IC 6.1.6. The objective of this flow is to increase layout productivity through improved routing functionality aimed at block-level interconnects. This flow enables users to quickly connect block pins in a structured topology. Includes documented tutorial and database.
10. Stamping Conflict Debugging in LVSDE
Resolving stamping conflicts has remained an area of challenge for the designers. The Stamping Conflict Debugger is aimed at easing this process. This RAK is a workshop on the Stamping Conflict Debugger to help new users learn and use this feature more effectively. Includes documented tutorial and database.
11. PVS Interactive Short Locator
This is a workshop on the PVS Interactive Short Locator Application. You will learn how to find shorts using the Interactive Short Locator, confirm the cause of the short without modifying the layout, add additional labels to help narrow down the shorted paths, resolve multiple labels shorts, and resolve shorts between unlabeled nets. Includes documented tutorial and database.
12. How to get the list of output signals and expressions set in ADE L and ADE XL session using SKILL?
Skill code for both ADE L and ADE XL to obtain the saved output signals and expressions.
13. How to create a device check expression for model or primitive
The device check UI can be confusing. This solution gives step-by-step instructions on how to set up a device checking expression for all devices which use a specific model or subcircuit.
14. How to read/load design variable from a text file to ADE window?
Skill code to read design variable name/value pairs and load the setup into ADE.
15. SKILL Example of OSM Object Sensitive Menu
Object or context-sensitive menus can be very handy. Here's an example of how to define your own.