Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
The Virtuoso Analog Design Environment XL Monte Carlo sampling methods are Random, Latin Hypercube, and Low Discrepancy Sequence. More accurately, Spectre provides the engine and ADE XL interfaces with the simulator to complete the Monte Carlo analysis task. Random is the standard random sampling method. Latin Hypercube (LHS) is an enhanced method that converges faster. Low Discrepancy Sequence (LDS) is the most recently developed method. Experimental results that compare the three methods are shown in the figure below.
Phase Margin of an op amp is measured and the mean error is compared to the golden result of 100K Monte Carlo samples. Each data point represents the result of 20 independent trials. The mean error is:
This is only one example but, in general, LHS and LDS results are found to be comparable. An advantage of LDS over LHS is that it is compatible with the ADE XL feature to automatically stop the Monte Carlo run given a yield estimate target. Provide a yield target and Monte Carlo will stop performing simulations when the design is either found to exceed the target or found to be low yield. This saves time by not running any more simulations than necessary based on the specified significance level. If needed you can loosen the significance level to get results faster or increase the level depending on your requirements.
Once the Monte Carlo results are available, statistical corners can be created. In ADE XL you can create a statistical corner from any of the simulated samples. There are several options to create the corner, including selecting a point on the histogram, creating a corner out of the worst sample, or by percentile.
ADE XL saves only the relevant information such as seed, sequence number, sampling method, etc. with the corner. Spectre can then recreate the statistical parameter values for the corner from this information. This type of corner is efficient and does not require that all the statistical parameter data for each sample is saved in Monte Carlo. The downside is that some changes to the design topology such as the addition of a new instance to the schematic can invalidate the corner. The simulator can no longer recreate the same set of statistical parameter values when simulating the statistical corner. Two types of statistical corners are possible in ADE XL with version IC6.1.6 ISR6; a corner with the sequence info saved, or a corner that contains all of the statistical parameter values. The values-based corner is more robust in the face of these minor design changes. The new instance added to the design does not invalidate the existing statistical corner of this type. The user can choose which corner type better suits their needs.
All of the above methods define the corner by one of the simulated Monte Carlo samples. To create a 3 sigma statistical corner you must have simulated a large number of samples. A new ADE GXL feature to be released with IC6.1.6 ISR6 addresses this problem. The goal is to create a k sigma statistical corner quickly (by default 3 sigma - you can specify the yield-in-sigma target) without the need to run thousands of simulations. The fast 3 sigma corner flow is to:
A minimum of 1 and a maximum of 11 extra simulations per corner are needed for this step.
The fast 3 sigma corner algorithm estimates the probability density function (PDF) of the performance distribution maintaining accuracy for non-normal distributions. The specification target value is computed from the PDF estimate.
A statistical corner is then created that matches the target spec value. There can be multiple corners that meet this criteria. This method finds the most representative corner by minimizing the distance to the nominal point. This representative corner has a greater probability to occur. Now the statistical corner can be used for further analysis of the design. Look for this feature in ADE GXL in the next IC6.1.6 release.
CCR 1247383 is now in state Checked_In and is scheduled for release in IC188.8.131.520.7 and ICADV12.1.500.9.
Thank you for highlighting this issue and the need to continue to push on capacity and performance limitations. The performance focus now is on very large circuits - the two most recent CCRs mentioned. The referenced solution was created in 2008 for IC6.1.3 and the older CCR fixed. Since then Monte Carlo performance has been greatly improved. Designs that were difficult to work with in IC6.1.3 are easily manageable in the more current versions.
The robust statistical corners and the fast 3-sigma corner flow are extremely welcome additions to the statistical analysis tools available in ADE. Both require saving the mismatch parameters of the Monte Carlo samples. Unfortunately, this currently causes an extreme slowdown of ADE XL during plotting or updating results (see support.cadence.com/.../cos ), which would make it practically impossible to use these new features for larger circuits. CCRs 557042, 1247383, and 1249170 have been filed for these issues. I hope that it will be possible to fix these problems in IC6.1.6 ISR6.