Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Anyone who has ever played a musical instrument knows how hard it can be to keep the instrument in tune when subjected to variations in weather conditions. Heck, in 2009, Yo-Yo Ma and friends (sorry, he gets top billing because I used to play the cello) pantomimed their performance at the Presidential Inauguration because their instruments wouldn't function properly in the frigid temperatures. Guess they didn't want to risk sounding like my seventh-grade orchestra in front of that large an audience.
Well, we've been talking a lot in this blog recently about the problems caused by the effects of variation on circuit design, and the risks of being "out of tune" can be just as great when it means your chip is late or doesn't work properly.
Today we're going to talk about some of the features available in the Virtuoso Analog Design Environment GXL (ADE GXL) to help you tune your circuit to overcome the effects of variation on circuit performance. Let's start by putting things in the context of an overall flow that looks like this:
The basic idea here is that you start with a test setup in ADE XL, which can consist of multiple testbenches, each with a set of output measurements and design specifications. Then you add the relevant corners, which will cover the limits of the design performance across which you need to optimize. These can be your standard PVT corners, they can be a critical subset of corners generated using the ADE GXL Worst Case Corners analysis, or they can be statistical corners generated from a Monte Carlo analysis to capture 3-sigma or other outlying statistical behavior for each of your design specifications.
One of the keys to getting the most out of the circuit-tuning capabilities in ADE XL and ADE GXL is device parameterization. I've written about this feature before, but to recap, the Variables and Parameters Assistant in ADE XL allows you to create parameters for any device properties and vary them at will without having to edit the schematic. You can also incorporate critical device matching and ratioing relationships.
The "Create Parameter Range" option will automatically create a +/-% range on any parameters, which makes sensitivity analysis and optimization a snap.
Sensitivity Analysis in ADE GXL allows you to get a good idea of the criticial devices in your circuit and their effects on design performance. With only a few targeted simulations, you can find out which devices in your circuit have the most impact on each of your design specifications, as well as how changing a device size whether changing a device size to improve one spec will adversely change the other specs. Device parameterization makes it quick and easy to evaluate "what-if" scenarios until your desired performance is achieved.
The optimization algorithms in ADE GXL have been proven within our customer base for many years. The optimizer works across all the multiple testbenches, specifications, and corners you already have set up, including the worst-case PVT and statistical corners you have defined to capture the extreme boundaries of your circuit behavior. Device parameters are intelligently varied over the ranges you have defined until all design specifications have been met. Simulations are distributed using ADE XL's job distribution system to maximize the efficiency of the analysis.
ADE GXL provides four local optimization algorithms: BFGS (recommended for most common analog circuits), Conjugate Gradient, Brent-Powell, and Hooke-Jeeves. Use these when you have a reasonable degree of confidence in your initial circuit starting point values. If you aren't sure of your starting point, use Global Optimization, which will perform a much broader exploration of the design space to find viable circuit solutions.
Several additional optimization-based run modes are available, including Size Over Corners to efficiently optimize over a large number of corners and Improve Yield, which combines Monte Carlo analysis and automatic statistical corner creation with iterations of circuit optimization to center your design within statistical process and mismatch variation.
"The proof of the pudding", as they say, "is in the eating," so the final step in our big red PowerPoint SmartArt arrow above is to verify the results of the circuit tuning. This may involve running a final simulation across all PVT corners or a final Monte Carlo analysis to verify the optimized design can overcome the effects of all types of variation.