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Plenty to keep you busy this month. Lots of RAKs, videos, and new Quick Start Guides and FAQs.
1. Using Annotation Browser with Virtuoso IPVS
Learn how to invoke the Annotation Browser and have it always appear docked to a specific location of the layout window, how to customize the Annotation Browser, and how to automatically set the visibility of the error markers.
2. AMS Designer INCISIVE Command-line Flow Use Model (updated)
Provides an overview on how to run mixed-signal simulations from the command line using the irun command.
3. Spectre PSPICE Netlist Support
Provides a means for designers to analyze IC and PCB components together in the same simulation by including PCB components in PSPICE format into a Spectre integrated circuit simulation.
Rapid Adoption Kits
4. Analog Design Environment XL (ADE XL) Workshop (updated)
Virtuoso Analog Design Environment XL provides a multi-test simulation environment for thorough design validation, extensive design exploration, IP reuse, and early insight into manufacturing variability. This material has been designed to highlight many of the features as well as key functionality of ADE XL. Includes new features in ADE XL up through IC 6.1.6 ISR3.
5. Virtuoso Visualization and Analysis (ViVA) (updated)
The Virtuoso Visualization and Analysis tool is an analog/mixed-signal waveform viewer providing the means to thoroughly analyze the data generated by circuit simulation. Learn how to use it either as a standalone tool or as an integrated part of the Virtuoso Analog Design Environment (L and XL). Includes new features in ViVA up through IC 6.1.6 ISR3.
Module generators are designed to provide a way to generate multiple Pcell instances into a complex, highly matched, structured array. With the Modgen tool, you specify the devices to be arrayed, then specify an interdigitation pattern, and insert dummy devices, body contacts, and guard rings. Finally, you control the routing style and generate internal routing geometry.
7. Virtuoso IPVS
Virtuoso IPVS is a mechanism where the PVS verification tool is tightly integrated with the Virtuoso platform. This RAK includes an introduction to Virtuoso IPVS and covers how to get started, the different modes of Virtuoso IPVS, how DRC violations are created and displayed for each mode, and how to customizde the rules for your design.
8. Static and Dynamic Checks (updated)
This material describes the usage of the Spectre APS/XPS static and dynamic design checks available in MMSIM13.1.1. These checks may be used to identify typical design problems including high impedance nodes, DC leakage paths, extreme rise and fall times, excessive device currents, setup and hold timing errors, voltage domain issues or connectivity problems. While the static checks are basic topology checks, the dynamic checks are performed during a Spectre APS/XPS transient simulation.
9. Introduction to Device Safe Operating Area (SOA), Circuit Conditions, and Asserts Workshop
This material highlights some of the ways that the user can set up and check for circuit conditions, perform device checking, and handle operating regions checks.
10. Mismatch Contribution
Mismatch Contribution analysis is a Monte Carlo post-processing feature that helps in identifying the important contributors to mismatch variation. You can then modify the identified devices in the design to make the design less sensitive to device mismatch variation.
11. Shortcuts to Improving Productivity Series
A three-video series describing shortcuts for improving productivity in Virtuoso Schematic Editor (VSE). Includes Editing Canvas (tips for quicker schematic drawing and editing), Customization, and Setting Colors and Backgrounds.
12. IC6.1.6 Pin-to-Trunk Block-Level Routing Series
A three-video series describing pin-to-trunk block-level routing. Includes Basics, Using Pin-to-Trunk Routing to Route Between Blocks, and Pin-to-Trunk Routing Using the Finish Trunks Command.
13. IC6.1.6 Pin-to-Trunk Device-Level Routing Series
A four-video series describing pin-to-trunk device-level routing. Includes Basics, Pin-to-Trunk Routing with Wire Assistant Overrides, Pin-to-Trunk Routing with Routing Scope and Via Control, and Pin-to-Trunk Routing Using the Finish Trunk Command.
14. What's New(-ish) in ADE XL in IC616 ISR3?
Discusses new features in ADE XL in IC6.1.6 ISR3, including the ability to more easily debug individual Monte Carlo sample points, adding user-defined columns to the outputs tables, more efficient use of disk space, and performance improvements.
15. Keeping Your Circuit in Tune: Sensitivity Analysis and CIrcuit Optimization
Gives an overview of how to use sensitivity analysis and circuit optimization in Virtuoso Analog Design Environment GXL (ADE GXL) to efficiently tune your circuit over corners and statistical variation.
16. What's New in Virtuoso ADE XL in IC616 ISR6?
Discusses new features in ADE XL in IC6.1.6 ISR6, including corner export/import to CSV, creation of K-sigma corners from Monte Carlo results, the ability to add user notes, cancelling selected tests and corners, and value-based statistical corner creation.
Support and Documentation
17. Cadence Online Support Release Highlights
Describes recent enhancements to the Case Creation Pages and Design IP Email interface.
18. FAQs and Quick Start Guides added to the Virtuoso IC 6.1.6 documentation set
The following documents have been added or updated in various IC6.1.6 ISRs to supplement the existing Virtuoso documentation set. They cover a range of topics including FAQs, Quick Start Guides, and process flow information for particular product areas.
19. How to turn on AMS UNL in IC 616 ISR6
The new AMS Unified Netlister (AMS UNL) was released in IC 6.1.6 ISR6. Here's how to enable it.