Analog/Custom Design

Spectre 26.1 Release Now Available

2026-10-20T00:20:00Z

We are pleased to announce the availability of Spectre®︎ 26.1, delivering innovations across hardware acceleration, core simulation technologies, and advanced solution flows. This release helps designers improve simulation performance, accelerate variation analysis, strengthen reliability verification, and address increasingly complex power, thermal, and radiation-aware design challenges.(read more)

Virtuoso AI Studio: Finding Specific Y-Values with Vertical Markers

2026-10-16T11:00:00Z

Tired of manually searching waveforms for specific signal values? Read this blog to learn how vertical markers help you quickly locate every occurrence of a specific y-value across analog traces or bus signals, eliminating manual searches. With support for selective searches and keyboard shortcuts, you can analyze waveforms faster and more efficiently.(read more)

Virtuoso AI Studio IC26.1 Now Available

2026-10-14T08:00:00Z

Virtuoso AI Studio IC26.1 production release is now available for download.(read more)

When AI Becomes Part of Your Analog Design Workflow

2026-10-13T15:00:00Z

If you design analog or mixed-signal circuits, each silicon generation asks you to do more. Advanced nodes mean tighter margins, new device behaviors, stricter design rules, and deeper interaction between the circuit, layout, simulation, and verification tasks. Meanwhile, schedules keep shrinking. The time problem is exacerbated by the engineering effort required to set up the EDA tools themselves: creating testbenches, writing scripts, setting up simulations, analyzing results, debugging failures, and repeating the process as requirements change.

This is where agentic AI can help: by reducing the EDA burden so engineers can focus more of their time on IC design, engineering judgment, and design robustness.

Cadence Virtuoso AI Studio, when paired with the Cadence ViraStack AI Super Agent, brings agentic AI directly into the analog and mixed-signal design environment. Instead of treating AI as a separate assistant, Virtuoso AI Studio places it alongside the tools and design context engineers already use, enabling AI to move from providing general answers or optimizing individual tasks to executing and coordinating parts of the design workflow.

Turning Design Intent into Action

Testbench creation illustrates the difference.

A designer may know exactly what needs to be characterized, but translating that requirement into stimuli, measurements, analyses, operating conditions, and simulation configurations can take considerable effort. The same applies when an analysis must be repeated across multiple conditions or modified as the design evolves.

In Virtuoso AI Studio, you can use natural-language interaction to initiate these activities within the design environment, then inspect and refine the resulting setup rather than building every element manually.

See the ViraStack AI Super Agent create a Virtuoso testbench from a natural-language request:

The same approach applies to scripting. You can describe the intended task and have the ViraStack AI Super Agent generate and refine Cadence SKILL code for the Virtuoso environment. Specific Virtuoso API information and design context help make the generated code relevant to the actual task rather than simply plausible, providing a 95% productivity improvement over manual efforts.

Migration Is Where Agentic Workflows Become Powerful

Technology migration is a particularly good example of why workflow-level automation matters.

Moving an analog design to a new process isn't simple device substitution. Device characteristics such as power, sizing, and operating points may need adjustment—constraints can change, and layout requirements can introduce additional dependencies. A migrated circuit that looks structurally correct may still require substantial optimization before it meets updated specifications.

The traditional workflow involves repeated topology mapping, device and constraint translation, parameter adjustment, simulation, analysis, and correction.

The ViraStack AI Super Agent's design migration agent is designed to assist with this sequence, including topology mapping, device scaling, and optimization across technologies.

Cadence has demonstrated the approach in a 6GHz analog/RF PHY migration flow, achieving 60% faster design closure. The value lies in connecting the steps that traditionally require engineers to move between tools, analyses, and iterations manually.

Advanced Engines for Physical Implementation and Optimization

Agentic workflows extend beyond schematic-level tasks into physical implementation and optimization. With ViraStack AI Super Agent, specialized agents coordinate layout, physical verification, extraction, and post-layout optimization using the underlying EDA engines. Multimodal input allows a floorplan to be generated from an image, helping bridge the communication gap between design and layout engineers. The agent proposes placement for review and generates the floorplan only after the engineer approves it.

The underlying layout engine identifies circuit structures in the schematic and generates constraints to guide layout generation. It produces multiple prototypes that include both placement and routing, giving engineers alternatives to inspect and compare. ViraStack AI Super Agent analyzes the candidates and highlights tradeoffs such as the smallest area, fewest opens, and a balanced result, helping engineers choose the appropriate starting point.

Physical verification follows the same engineer-guided approach. Agents can check the full layout for design-rule violations, report the findings, and recommend corrections, while engineers decide which violations to address. For post-layout optimization, the agent checks the DSPF setup, identifies failing specifications, and invokes optimization that accounts for parasitic changes without requiring layout regeneration. Engineers can then request further analysis or debugging of the results, reducing manual coordination across the physical implementation flow while retaining control of design decisions.

Domain Context Matters

An AI system for analog design needs more than a natural-language interface. It needs to understand the design, the tools it operates, and the methodology behind the task. Analog and RF circuits contain relationships between topology, devices, constraints, operating conditions, measurements, and methodology that cannot be captured by simply translating a sentence into an EDA command.

The ViraStack AI Super Agent is built around that context. Its built-in skills and Virtuoso-specific knowledge give agents access to design information and Virtuoso APIs, while the mental model captures design intent, circuit functionality, and methodology knowledge in a structured format. This helps prevent AI hallucinations, improves the accuracy and speed of agent execution, and reduces token usage.

The IP Catalog extends this foundation by supporting the reuse of proven designs and providing a built-in library of hundreds of analog building blocks. Together, these capabilities give agents structured design knowledge that can be applied across workflows, helping make design automation more accurate and efficient.

Agents on Top of Proven EDA Engines

Virtuoso AI Studio continues to rely on technologies such as Cadence's Circuit Simulation and Pegasus Verification Platform, along with the broader portfolio of silicon-proven, foundry-qualified technologies that support design, layout, and optimization.

The AI layer operates on top of that foundation. Agents can determine what action is needed, invoke the appropriate capability, analyze results, and coordinate what happens next. AI may identify a potential issue or suggest a change, but circuit behavior must still be established through simulation and verification.

Agents orchestrate proven EDA engines to analyze and verify. Engineers make the final decisions.

Scaling Expertise Across the Organization

Analog design knowledge is difficult to codify. It lives in design libraries, scripts, methodologies, and in the experience of senior engineers.

Experienced designers can use AI as a force multiplier, delegating repetitive setup, analysis, scripting, and workflow coordination while focusing on architecture, topology, and difficult tradeoffs. Enterprise AI Needs Enterprise Controls

Custom design environments contain proprietary circuit structures, libraries, process information, methodologies, and IP. Any AI capability used in production must, therefore, fit within an organization's security and deployment requirements.

Virtuoso AI Studio is built on the Cadence JedAI Solution and supports secure infrastructure, including cloud-enabled and on-premises deployment models. The ViraStack AI Super Agent can also work with customer-specific design knowledge and proprietary libraries within the customer's controlled environment.

What Changes for the Analog Designer?

Engineers will continue to define what a circuit must achieve, make architectural and topology decisions, evaluate tradeoffs, interpret results, and approve changes. Agents can increasingly take on the work surrounding those decisions, from setting up analyses and generating testbenches and scripts to running defined workflows, analyzing results, supporting migration, and coordinating related tasks.

For that approach to work in custom design, AI needs more than intelligence. It needs domain expertise, established design methodologies, and proven EDA engines grounded in decades of real-world silicon design. Virtuoso AI Studio brings these capabilities together in the familiar Virtuoso environment, with the ViraStack AI Super Agent providing the agentic intelligence and Cadence EDA engines providing the engineering foundation. For analog designers, the opportunity is clear: less time spent managing the mechanics of the design flow means more time for the engineering decisions that matter.

Explore Cadence Virtuoso AI Studio and see how the ViraStack AI Super Agent can support the custom design workflow.

Powering the Future of Sustainable IoT: World's Lowest-Power MCU

2026-10-05T13:55:00Z

As AI, smart infrastructure, and connected devices spread into more parts of everyday life, the Internet of Things is entering another phase of growth. IoT analytics project that the number of connected IoT devices will exceed 40 billion by 2030, across buildings, industrial automation, healthcare, agriculture, and smart city infrastructure.

The problem is not connectivity. It is power.

Batteries remain the default answer for most IoT devices, but the costs accumulate quickly. A battery must be manufactured, transported, installed, replaced, and eventually disposed of. Multiply that by thousands of sensors in a building, or millions of devices across a product category, and battery life becomes an operational and sustainability problem rather than a line item on a datasheet.

Norwegian semiconductor company ONiO has taken a different approach: instead of asking how long a battery can last, it is designing connected devices to use energy already available in their environment.

Reimagining IoT Without Batteries

ONiO was founded around a simple but demanding idea: make useful, connected products without assuming that a battery has to be there.

Its ONiO.zero platform can harvest ambient energy from sources such as radio-frequency signals, light, thermal gradients, and vibration. In suitable applications, that energy can replace the battery entirely.

The platform is designed to work with a broad range of energy sources rather than one specific harvesting technology. ONiO.zero integrates an on-chip RF energy harvester and supports photovoltaic, thermal, kinetic, and piezoelectric sources. It operates across a supply range from 250 mV to 3.0 V and can be powered by harvested energy, capacitors, supercapacitors, secondary cells, or conventional batteries. That gives developers room to choose the energy architecture that fits the product.

ONiO.zero brings computing, wireless connectivity, memory, security, and power management together in a highly integrated wireless microcontroller. The difficult part is making all those functions useful inside the tiny energy budgets that harvesting can provide.

Setting New Standards for Ultra-Low-Power Computing

Battery-free operation starts with a very small power budget.

Independent EEMBC ULPMark®-CoreMark® results provide a useful reference point. In the published ONiO entry, energy, fixed voltage is 178 at 3.0 V and energy, best voltage is 181, also at 3.0 V; the performance score is 124. Those are the benchmark scores. ONiO's separate 22 µW/MHz figure describes power while running CoreMark from non-volatile memory at 4.1 CoreMark/MHz.

The device uses a custom 16/32-bit RISC-V RV32IMC processor, designed in-house rather than licensed, and combines that processing capability with the ability to cold-start from less than 1 µW of available power and sleep at well below 1 µW. For energy-harvesting products, those states matter as much as headline compute efficiency: the device must wake, do useful work, communicate, and return to sleep without exhausting the energy that has been collected.

ONiO.zero also integrates standards-based low-energy 2.4 GHz wireless connectivity, including IEEE 802.15.4 support for protocols such as Matter, Thread, and Zigbee RF4CE, along with sensor interfaces, energy-harvesting functions, and built-in security. Hardware-accelerated AES encryption, SHA-256 hashing, and a true random number generator are implemented in silicon, so security does not have to be treated as an external add-on.

The aim is not low power by removing functionality. It is useful wireless computing inside an unusually small energy envelope.

Sustainability by Design

That changes more than the energy bill.

Battery replacement can be one of the largest lifecycle costs in an IoT deployment, especially when devices are numerous, remote, hazardous to reach, or simply inconvenient to access. Harvesting energy from the surrounding environment can reduce maintenance, lower the total cost of ownership, and remove material from the eventual waste stream.

Consider electronic shelf labels. A mid-size supermarket can operate on the order of 50,000 labels, with two-coin cells in each label and a service life of around 18 months. That is roughly 100,000 batteries in one store, followed by another replacement cycle when those cells reach end of life. Remove the battery and you also remove much of the replacement labour and disposal that comes with it.

Elimination is not the only outcome. Where the available energy cannot carry the whole load, the same power architecture extends a conventional cell instead of replacing it, by roughly five to ten times. A coin cell that would have been changed every eighteen months can instead last the service life of the product. Across tens of thousands of devices that removes most of the same batteries and most of the same replacement labour, and it applies to a far wider range of products than harvesting alone.

The same logic applies across a wide range of IoT deployments:

Smart homes and intelligent buildings
Environmental monitoring
Precision agriculture
Healthcare and wearable devices
Industrial IoT
Logistics and asset tracking
Smart city infrastructure

For some of these applications, battery-free operation is not merely a more sustainable version of the same product. It can make deployment practical in places, quantities, or form factors where routine battery replacement would otherwise be too expensive.

Engineering Innovation Powered by Cadence

Reaching those power levels is a system-level design problem. Processing, radio, memory, security, analogue circuitry, and power management all must be optimized together, across both analogue and digital domains. An improvement in one part of the device is not enough if another part consumes the harvested energy first.

ONiO used a comprehensive Cadence design flow to manage that complexity: Cadence Virtuoso Studio for analogue and mixed-signal design, the Innovus Implementation System for digital implementation, Xcelium Simulator and Jasper Formal Verification for verification, Tempus Timing Signoff for timing closure, and the Pegasus Verification System for physical verification.

ONiO CTO Vemund Bakken says the company selected Cadence as its sole EDA partner because of the breadth and integration of the environment and flexible licensing. Having tools available on tap is mandatory for a company like ONiO, where almost every single tool Cadence offers are used during the design cycle. These include analog capture and simulation in Virtuoso, synthesis with Genus, timing closure with Tempus, and place and route using Innovus.

Building a More Sustainable Connected Future

Extending battery life and removing the battery are the same engineering problem solved to different depths. What does not scale, in a world of billions of connected devices, is the assumption that somebody will come back to change them.

Energy harvesting changes the design question. Instead of sizing a product around the energy stored in a battery, developers can begin with the energy available in the environment and design the system to live within it. That is a harder constraint, but it can also remove maintenance cycles and open deployment models that conventional battery-powered devices struggle to support.

ONiO.zero shows how ultra-low-power computing, wireless connectivity, security, power management, and multi-source energy harvesting can be brought together on one platform. Cadence software and support have been part of the engineering path behind that integration, helping ONiO turn battery-free IoT from an aspiration into a measured semiconductor result.

As sensing becomes more pervasive, that shift matters: fewer batteries to replace, fewer batteries to discard, and more freedom in where connected devices can operate.

The One Transistor That Became a Thousand - Without You Drawing It Twice

2026-09-30T13:45:00Z

Drawing every transistor variant by hand doesn't scale — change the width, the fingers, or the channel length, and you're redrawing from scratch. Parameterized Cells (Pcells), written in the SKILL®︎ language, solve this by letting you define a transistor once and generate every variation from parameters.(read more)

From Waveform to Root Cause: Debugging Mixed-Signal Designs with SimVision MS

2026-09-29T10:15:00Z

Learn how SimVision MS connects waveforms, mixed nets, connect modules, schematic tracing, OOMRs, and solver diagnostics for effective debugging.(read more)

Fix It Faster: The Secret Virtuoso Tool You're Not Using

2026-09-29T09:50:00Z

Virtuoso suddenly slows down. Do you restart, call IT, or keep guessing? Before you do any of those, check its pulse.

Have you ever been in the middle of a Virtuoso session when a familiar command takes longer than expected, a design opens slowly, or the entire session stops responding? The immediate question is usually the same: Is the issue coming from Virtuoso, the design, the environment, or the surrounding system?

Instead of restarting the session or switching between multiple debugging utilities, open 'Diagnostic Center.' It brings performance and data-integrity checks into a single unified interface, helping you investigate the environment, library access, design data, and system resources. Start with 'Health Monitor' to check Virtuoso's pulse, determine whether the slowdown is related to the tool or to CPU, memory, or network activity, and collect the right debugging evidence to guide your next step.

Health Monitor: Start with the Pulse

Think of health monitor as the pulse monitor for Virtuoso. It continuously monitors Virtuoso and system health while you work, then signals when a performance issue arises, whether the source is Virtuoso or a non-Virtuoso resource such as CPU, memory, or network.

Its real-time status bar displays signals, the entry command, and a short message. The 'Advanced Form' provides CPU, memory, process, and network information, helping you distinguish tool behavior from a system-resource issue. If the slowdown persists, record callstacks to capture what Virtuoso is doing. If the session freezes, the user should terminate Virtuoso using the health monitor instead of the 'kill' command when Virtuoso is in a hang state.

Additional Checkers

Once the health monitor points you in the right direction, the diagnostic center's additional checkers provide targeted context through the following features:

Library: checks library information and access issues.
Design: checks recursion, statistics, memory usage, duplicate objects, database issues, constraints, and edit locks.
Environment: examines environment variables, graphics, remote desktop, licensing, system information, and data storage.
SKILL: provides profiling and replay for specialized debugging.
Data integrity: checks layout, constraints, and database integrity.

Debug Smarter, Not Longer

Over time, the diagnostic center becomes a natural part of the Virtuoso workflow. It provides a repeatable process: identify the signal, determine whether the issue is inside or outside Virtuoso, collect the right evidence, and act on the data.

So why are you waiting? Start using the health monitor along with additional target checkers to quickly identify performance issues. I believe this diagnostic center will help you spend less time troubleshooting and more time designing.

Do You Have Access to the Cadence Support Portal?

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On the Cadence Support portal, select 'Register Now' and provide the requested information on the registration page.
You will need an email address and host ID to sign up.
If you need help with registration, contact support@cadence.com.

To stay up-to-date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails.

If you have questions about courses, schedules, online, public, or live onsite training, contact us at Cadence Training.

Become Cadence Certified

You can become Cadence Certified once you complete the course and share your knowledge and certifications on social media channels. Go straight to the course exam at the Learning and Support Portal.

Note: Some of the above links are accessible only to Cadence customers who have a valid login ID for the Cadence Learning and Support Portal.

Take the Accelerated Way

The faster you finish your online training, the sooner you can claim your Digital Badge. Want to know how accelerated learning works? Our video walks you through the pre-quiz, navigation, and essential features. This is just the beginning. We're regularly adding new Accelerated Learning titles. Accelerated learning courses are marked with this symbol in our Learning Maps.

Related Resources

Training Bytes (Videos)

What is Diagnostic Center?

Dsiplaying the Diagnostic Center Form

Best Practices For Troubleshooting Virtuoso Sessions

Diagnostic Center: Performance Checkers

Product Manual

Virtuoso Studio Environment User Guide IC25.1

Virtuoso Studio What's New

Online Courses

Virtuoso Layout Design Basics

Virtuoso Layout Onboarding Training

Virtuoso Layout Pro: T3 Basic Commands

Virtuoso Layout Pro: T4 Advanced Commands

Virtuoso Studio Features

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About Knowledge Booster Training Bytes

Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars that are available in the learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material on a regular basis.

Veena G P

On behalf of the Cadence Training Team

Make the Right Layout Decisions Earlier

2026-09-28T11:30:00Z

Explore how Virtuoso Design Planner brings hierarchy, connectivity, placement, and congestion information into early layout planning, helping teams build and refine a design plan before detailed implementation.(read more)

Earn, Validate, and Showcase Your IC Design and Verification Expertise

2026-09-25T05:07:00Z

Turn technical learning into trusted, shareable recognition with Cadence training, Training Bytes, and digital badges(read more)

Spectre MDL: Turn Simulation Results into Reusable Measurements

2026-09-11T05:18:00Z

Running a simulation is only half the job. Engineers must also extract useful measurements from the resulting waveforms.

Imagine characterizing an amplifier across different voltages and temperatures. Manually checking gain, rise time, duty cycle, and threshold crossings for every run can become repetitive. Spectre Measurement Description Language, or Spectre MDL, helps automate this work.

What Is Spectre MDL?

Spectre MDL is a scripting and measurement language that works with the Spectre Circuit Simulator and Virtuoso Visualization and Analysis.

It can help you:

Create reusable measurement definitions
Run simulations in batch mode
Pass parameters into measurements
Automate sweeps using loops
Search for circuit-performance boundaries
Evaluate additional measurements from existing simulation results

A Simple Example

An engineer may want to measure the DC gain and zero-dB crossing frequency of an amplifier:

The measurement alias connects an analysis with one or more measurement expressions. It can then be reused in compatible simulation flows.

Why Use Spectre MDL?

Reuse Measurement Logic

Measurements such as gain, rise time, fall time, RMS, duty cycle, phase margin, and threshold crossing can be defined once and reused.

Automate Characterization

The foreach statement supports repetitive simulations and sweeps. The search statement varies a parameter until a specified circuit condition is reached.

Reduce Unnecessary Simulation

The autostop feature can stop a transient simulation after sufficient data is available for the requested measurements.

Measure Existing Results

Postprocessing mode lets you evaluate updated or additional measurements using an existing simulation results database, provided the required signals were saved.

Spectre MDL turns measurement intent into an executable and reusable part of the simulation flow. Instead of repeatedly inspecting waveforms, engineers can automate measurements, sweeps, searches, and postprocessing. For anyone working with Spectre simulation and analog characterization, MDL offers a practical path from waveforms to repeatable results.

Want to Learn More?

For lab instructions and a downloadable design, enroll in the online training courses of your interest:

Spectre Simulator Fundamentals S4: Measurement Description Language Training

Training is also available as a blended or live class.

Note: Access to some training links is limited. They are accessible only to the Cadence customers who have a valid login ID for the Cadence Learning and Support Portal.

Do You Have Access to the Cadence Support Portal?

If not, follow the steps below to create your account.

On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
You will need an email address and host ID in order to sign up.
If you need help with registration, contact support@cadence.com.

To stay up-to-date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails.

If you have questions about courses, schedules, online, public, or live onsite training, reach out to us at Cadence Training.

Become Cadence Certified

Cadence Training Services is now offering digital badges for its training courses. These badges indicate your proficiency in a specific technology or skill, allowing you to validate your expertise to potential employers or managers. You can easily add these digital badges to your email signature or to your social media profiles, such as Facebook or LinkedIn, to highlight your skills and expertise. To become Cadence Certified, you can find additional information here. Go straight to the course exam at the Learning and Support Portal.

Related Resources

Training Bytes (Video Channel)

Spectre MDL (Video Channel)

Online Course

Spectre Simulator Fundamentals S4: Measurement Description Language Training

About Knowledge Booster Training Bytes

"Knowledge Booster Training Bytes" is an online journal that provides information about Cadence Training videos, online courses, and upcoming webinars that are available on the Cadence Learning and Support portal. This blog category offers direct links to these videos, courses, and other related materials on a regular basis.

Sai Darshan S Nishani

Sr. Education Application Engineer

From Simulation Data to a Clear Story: Meet the Datasheet Interface 2.0

2026-09-10T07:31:00Z

You have completed several simulations. Now you need to answer a simple question: Did the design meet its targets?

The information may be spread across tests, variables, corners, plots, and simulation histories. Reviewing each item separately can make an otherwise simple design review feel complicated. That is where the datasheet interface 2.0 becomes useful. It turns simulation information into a structured HTML report that is easier to browse, review, and share.

Why Do We Need a Datasheet?

Imagine that you are validating an amplifier across different operating conditions.

You may need to check:

Which test was executed?
What variables and parameters were used?
Which corners were simulated?
Did the results pass the target specifications?
Which waveforms need closer attention?

A datasheet consolidates this information into a single navigable report. It can include test information, variables, parameters, corner and model-group details, numerical results, and selected plots. The report is stored with the maestro view in ADE Explorer, ADE Assembler, and ADE Artist, appears in the data view assistant, and can be opened in a browser.

What Makes the Interface Easy to Read?

1. A Summary Before the Details

The results summary presents target, minimum, and maximum values together. Color coding makes the status easy to scan:

Green: Pass
Yellow: Near
Red: Fail

This helps reviewers identify results that deserve attention before opening detailed data.

2. Simple Navigation

Sections in the report are linked, and selecting a test name opens its detailed results. Readers can move from the overall summary to an individual test without manually searching through separate outputs.

3. Context Stays with the Result

The session summary can show test, state, simulator, variable, parameter, corner, and model-group information. This makes it easier to understand not only what the result was, but also which setup produced it.

4. Waveforms When They Matter

The datasheet can include waveforms for selected tests. It also supports open graphs, all graphs, or a saved plotting template. Quickplot data can be used for transient waveform images.

A Quick Real-World View

Suppose one corner produces a result close to the required specification.

Instead of opening several simulation windows, you can:

Notice the yellow status in the Results Summary.
Select the test name.
Review its variables, parameters, and numerical results.
Examine the associated waveform.
Return to the main report and continue reviewing.

The interface helps turn a large collection of simulation data into a short investigation path.

The video below gives you a detailed overview of the new datasheet interface.

The New Datasheet Infrastructure

Want to Learn More?

For lab instructions and a downloadable design, enroll in the online training courses of your interest:

Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis Training

Training is also available as a blended or live class.

Note: Access to some training links is limited. They are accessible only to the Cadence customers who have a valid login ID for the Cadence Learning and Support Portal.

Do You Have Access to the Cadence Support Portal?

If not, follow the steps below to create your account.

On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
You will need an email address and host ID in order to sign up.
If you need help with registration, contact support@cadence.com.

To stay up-to-date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails.

If you have questions about courses, schedules, online, public, or live onsite training, reach out to us at Cadence Training.

Become Cadence Certified

Cadence Training Services is now offering digital badges for its training courses. These badges indicate your proficiency in a specific technology or skill, allowing you to validate your expertise to potential employers or managers. You can easily add these digital badges to your email signature or social media profiles like Facebook or LinkedIn to highlight your skills and expertise. To become Cadence Certified, you can find additional information here. Go straight to the course exam at the Learning and Support Portal.

Related Resources

Training Bytes (Video Channel)

Virtuoso ADE Assembler (Video Channel)

Online Course

Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis Training

About Knowledge Booster Training Bytes

Sai Darshan S Nishani

Sr. Education Application Engineer

Virtuoso Studio IC25.1 ISR8 Now Available

2026-09-09T09:43:00Z

Virtuoso Studio IC25.1 ISR8 production release is now available for download.(read more)

From “Where Do I Click?” to Confident Virtuoso IC Layout Designer

2026-09-01T06:24:00Z

What if the moment you opened Virtuoso no longer felt overwhelming-but empowering?

You already know the fundamentals. You have mastered MOSFET theory, layout rules, and circuit behavior. On paper, everything adds up. But when it’s time to turn theory into silicon, there’s a critical gap no textbook prepares you for—the tool. That first Virtuoso launch can be intimidating: a blank workspace, multiple windows, unfamiliar terminology, and a quiet question running through your head—Where do I even begin?

This is exactly the challenge Virtuoso Layout Design Basics course is built to solve. In just two days, this course transforms beginners into confident Virtuoso users, guiding you step by step from launching the tool to building and managing real IC layouts. There’s no guesswork and no trial‑and‑error frustration—just a clear, structured path to productivity in the industry’s most widely used custom IC layout platform.

What truly sets this course apart is its strong focus on real‑world usability.

You're not simply learning isolated commands or menu options; you’re learning how layout designers actually work inside Virtuoso. Each concept is introduced in context, reinforced through hands‑on exercises, and tied directly to practical layout tasks you’ll encounter on real projects. As you gain experience, the interface becomes second nature, workflows are seamlessly intuitive, and the tool empowers you to excel without holding you back.

Whether you’re a new graduate, a schematic designer transitioning into layout, or an engineer looking to formalize your Virtuoso skills, Virtuoso Layout Design Basics provides a confident starting point. It replaces hesitation with clarity, uncertainty with structure, and “I’ll figure it out later” with “I know exactly what to do next.” And that confidence is what ultimately turns knowledge into progress—and designs into silicon.

What You’ll Learn in Virtuoso Layout Design Basics

By the end of this course, you’ll be able to:

Navigate the Virtuoso Design Environment with confidence: Launch Virtuoso, work with the Command Interpreter Window (CIW), and manage design data using the Library Manager
Understand and customize the Virtuoso user interface: Work efficiently with layers, objects, grids, palettes, assistants, bindkeys, and toolbars to match your layout workflow
Create and edit layout geometry using essential commands: Use selection, alignment, copy, stretch, via creation, and labeling commands to build clean, accurate layouts
Work smarter with hierarchy and reusable layout blocks: Edit hierarchical designs, remaster instances, and create top‑level layouts from existing cells
Manage layout data and databases effectively: Use Stream In and Stream Out to import or export GDSII files from/to the mask shop
Apply design‑rule‑driven editing concepts early: Get introduced to design‑rule‑aware layout practices and interactive routing workflows
Build real‑world confidence through hands‑on labs: Reinforce every concept with guided lab exercises that mirror real IC layout tasks

After completing this course, learners can continue building their layout skills through advanced training focused on efficiency, scalability, and real‑world workflows. The next steps progress from strengthening everyday layout editing skills to advanced productivity techniques and finally to constraint‑aware, connectivity‑driven design approaches used in production environments.

Related Courses

Virtuoso Layout Pro: T3 Basic Commands
Virtuoso Layout Pro: T4 Advanced Commands
Virtuoso Layout Pro: T5 Interactive Routing

Become Cadence Certified

You can become Cadence Certified once you complete the course and share your knowledge and certifications on social media channels. Go straight to the course exam at the Learning and Support Portal.

Note: Some of the above links are accessible only to Cadence customers who have a valid login ID for the Cadence Learning and Support Portal.

Do You Have Access to the Cadence Support Portal?

If not, follow the steps below to create your account.

On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
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Achieve Real-World Noise Simulation with Spectre Transient Noise Analysis

2026-08-18T13:30:00Z

From Ideal Signals to Real-World Behavior

In today's advanced analog and mixed-signal designs, first-pass silicon success requires more than just clean simulation results. Engineers often observe a disconnect between ideal simulations and real silicon performance—especially in applications like PLLs, SerDes, sigma-delta modulators, RF front ends, etc.

For example, even though a PLL has stable locking behavior in a transient simulation, it might exhibit unacceptable jitter and instability when fabricated.

Why Spectre Transient Noise Analysis is Essential

The Spectre Simulation Platform offers multiple noise analysis techniques, each suited to different circuit classes:

AC noise analysis → For linear, time-invariant circuits
Periodic noise (pnoise/hbnoise) → For nonlinear, periodic systems
Transient noise analysis → For non-periodic and nonlinear circuits

Visualizing Device Noise: The Spectral Picture

Before we set up a transient noise simulation, it helps to picture what device noise looks like in the frequency domain. The noise spectrum graph below summarizes the key features every analog/RF engineer must internalize:

Figure 1: Noise spectrum

A flat white-noise floor that dominates from mid to high frequencies, up to F_max
A 1/f (flicker) noise slope that rises sharply at low frequencies, below the 1/f corner
An additional n²/f component, highlighted to show higher-order low-frequency contributions
Clear boundaries at F_minand F_max, defining the bandwidth over which transient noise is simulated

Why This Matters For Your Design

Real silicon noise is never flat. However, it can have a constant noise curve. Flicker noise dominates close to DC and—through nonlinear mixing in oscillators and PLLs—folds back around the carrier as close-in phase noise and long-term jitter. Transient noise analysis can model the noise folding because it injects noise sources directly into the time-domain simulation of non-periodic, nonlinear circuits.

Figure 1 visually answers the introduction's question: 'why does my PLL lock cleanly in simulation but jitter in silicon?' The 1/f tail and its folding are the culprits, and appropriate choices for F_min and F_max ensure those mechanisms are represented in your simulation.

What This Training Covers

The Spectre Transient Noise Analysis in Virtuoso Studio course provides a structured blend of theory and hands-on expertise.

1. Fundamentals of Noise Analysis

Types of noise and their impact on circuits
Overview of Spectre noise analysis methodologies
Device noise modeling and spectral behavior

2. Transient Noise Concepts

Definition and purpose of transient noise analysis
Understanding computational challenges
Key parameters: Noise seed, noise F_max and F_min, noise contribution, power spectral density settings for performing the transient noise analysis

3. Simulation Setup in Virtuoso Studio

Configuring transient noise analysis in the Virtuoso ADE Explorer/Assembler
Working with simulation options and forms
Controlling accuracy and convergence parameters

4. Advanced Simulation Techniques

Running simulations with multiple runs
Statistical averaging
Generating and analyzing Power Spectral Density (PSD) using fourier analysis settings

5. Comparative Noise Analysis

Comparing:

Transient noise vs AC noise
Transient noise vs pnoise
Transient noise vs hbnoise

Helps engineers choose the right analysis for the right design problem.

6. Jitter Analysis and Time-Domain Insights

Understanding jitter mechanisms
Measuring jitter using transient noise
Measuring jitter using sampled periodic noise (pnoise)

Interactive Learning: Visualizing Noise Behavior

This training emphasizes visual and experiential learning:

Observe how noise evolves in time-domain waveforms
Analyze signal distortion and jitter visually
Compare different simulation methodologies side-by-side

This approach helps bridge the gap between theory and real-world design challenges. For more details, kindly navigate the training: Spectre Transient Noise Analysis in Virtuoso Studio.

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