Analog/Custom Design

Virtuoso Studio: Excellent XL – Analyze and Fix Connectivity with Analyzer

2026-06-15T12:41:00Z

Click here to see how Connectivity Analyzer helps you analyze connectivity markers and guide you toward fixes that can be applied directly from the tool.(read more)

Virtuoso Studio IC25.1 ISR6 Now Available

2026-06-10T05:04:00Z

Virtuoso Studio IC25.1 ISR6 production release is now available for download.(read more)

Virtuoso Studio: Excellent XL – How to Keep Layout XL Up to Date with Ease

2026-06-08T21:15:00Z

On‑canvas binding highlights provide color‑coded visibility of binding status across layout and schematic canvases, helping you quickly identify and fix inconsistencies. Click here to learn more.(read more)

Electrically Aware Design: Catch EM and IR Drop Issues Early with EAD

2026-05-26T03:30:00Z

As designs move to advanced nodes, interconnect reliability is pushed to its limits. Narrower metal widths, higher current densities, and dense routing significantly increase exposure to electromigration (EM)—a failure mechanism that can unexpectedly undermine long‑term chip performance and reliability. When these issues surface late, the cost is paid in rework due to increasing wire widths, via insertions, which in turn can result in placement changes leading to schedule slip.

This Virtuoso Layout for Advanced Nodes: T2 Electromigration course teaches you how to use Virtuoso’s EAD flow to prevent, find, and fix electromigration issues in your layout. By identifying problems early, you can avoid rework and develop the hands‑on reliability skills needed for advanced‑node design.

Why Electrically Aware Design Matters

Traditional layout workflows rely heavily on signoff‑stage checks to flag EM and IR‑drop issues. At advanced nodes, that approach is no longer sufficient. The EAD methodology integrates electrical analysis directly into layout creation, allowing designers to evaluate reliability continuously—not just at the end.

Electrically Aware Design (EAD) enables designers to analyze EM and IR drop issues during layout creation, using real-time simulation data to ensure electrically correct designs and avoid costly late-stage rework. Building on this, Virtuoso Simulation Driven Routing (SDR) takes it further by automatically sizing wires and vias based on current, helping achieve EM-compliant, reliable layouts with a true correct-by-construction approach.

This course shows how EAD enables:

Early visibility into current density and voltage drop risks
Faster convergence by analyzing partial layouts
Fewer late‑stage surprises and redesigns

By combining simulation data with layout intelligence, designers gain actionable feedback exactly when they need it most.

Key Topics Covered

After completing the course, you will learn how to:

Understand and apply the Electrically Aware Design flow
Execute simulations to create the electrical current data needed for EMIR checking
Optionally create datasets for EM and IR-drop analysis when simulation is not yet available
Perform pre-layout EM checks
Run RC parasitic extraction on partial and complete layouts
Create datasets for EM and IR‑drop analysis
Visualize parasitics and check for violations, such as cross talk coupling, using the EAD Browser
Run EM checks and resolve violations interactively
Re-simulate designs in ADE Assembler using extracted parasitics at any time during layout creation
Analyze lower-node complexities and layout-dependent effects (LDE)

These topics are reinforced through structured labs that closely mirror real-world advanced-node design challenges.

Who Should Take it?

This course is a great fit if you are:

A student (or early‑career engineer) aiming to build job‑ready skills in advanced‑node custom layout and reliability‑aware flows.
A layout professional working on analog/mixed‑signal/custom blocks who wants more confidence in EM/IR analysis and closure using Virtuoso^®EAD.

Conclusion

The Virtuoso Layout for Advanced Nodes: T2 Electromigration course empowers designers to move beyond late‑stage reliability checks and adopt a proactive, electrically aware layout methodology. By integrating EM analysis early and throughout the design cycle, teams can reduce rework, shorten schedules, and deliver more reliable silicon with confidence.

Enroll in the Course Virtuoso Layout for Advanced Nodes: T2 Electromigration to learn more about Electromigration (EAD Flow) in Virtuoso Studio.

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On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
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If you need help with registration, contact support@cadence.com.

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If you have questions about courses, schedules, online, public, or live onsite training, contact us at Cadence Training.

Become Cadence Certified

Cadence Training Services now offers digital badges for this training course. These badges indicate proficiency in a certain technology or skill and give you a way to validate your expertise to managers and potential employers. You can highlight your expertise by adding these digital badges to your email signature or any social media platform, such as Facebook or LinkedIn. To become Cadence Certified, you can find additional information here. Go straight to the course exam at the Learning and Support Portal. For more information, visit Cadence Learning and Support - https://support.cadence.com - Your 24/7 Self-Help Partner.

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The faster you finish your online training, the sooner you can claim your Digital Badge. Want to know how accelerated learning works? Our video walks you through the pre-quiz, navigation, and essential features. This is just the beginning. We're regularly adding new Accelerated Learning titles. Accelerated Learning courses are marked with this symbol in our Learning Maps.

Related Resources

Online Courses

Virtuoso Layout for Advanced Nodes

Virtuoso Layout for Advanced Nodes: T1 Place and Route

Virtuoso Layout Advanced Nodes: T2 Electromigration

Auto Place and Route (APR) for Virtuoso Studio – Device Level

Auto Place And Route (APR) for Virtuoso Studio – Standard Cell

Rapid Adoption Kit

Electrically-Aware Design Flow for Advanced Nodes

Simulation Driven Routing (Advance Node)

User Guide

Virtuoso ADE Assembler User Guide

Virtuoso Electrically-Aware Design Flow User Guide

For more information on Cadence circuit design products and services, visit www.cadence.com.

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Contact Us

For any questions or general feedback, please write to custom_ic_blogs@cadence.com.

About Knowledge Booster Training Bytes

Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars that are available in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material on a regular basis.

Sandeep O

On behalf of the Cadence Training Team

Liberate Trio: A Scalable Answer to Advanced-Node Characterization

2026-05-18T08:30:00Z

The Growing Pain No Library Team Can Ignore

If you're working on standard-cell libraries at 28 nm or below, you already know the math isn't in your favor.

At the 130 nm node, a typical library had fewer than 100 cells and a handful of PVT corners. Fast-forward to 16/14 nm and beyond, libraries now contain 1,200+ cells across 200+ PVT corners.

Every new SoC tape-out demands broader coverage for design robustness, and the characterization workload has exploded.

The question is no longer whether you need multi-PVT characterization; it’s how fast you can adopt it.

The chart below shows how both cell count and PVT corner count have surged at advanced nodes:

The Importance of Multi-PVT Characterization

Every standard cell must be characterized for timing, power, and noise across all approved PVT(Process Voltage Temperature) corners. This ensures reliable SoC operation under all conditions from fastest to slowest performance, across hottest and coldest temperatures, and varying voltage levels.

At advanced nodes, three forces collide:

More cells: Complex logic, multi-Vt variants, low-power cells
More corners: Tighter voltage/temperature margins, more process skews
Shorter schedules: Aggressive tape-out timelines leave no room for reruns

Multi-PVT characterization addresses all three by enabling parallel execution across corners, reducing redundant work, and ensuring consistency.

The Solution: Liberate Trio Built for Multi-PVT Scale

Liberate Trio is Cadence’s advanced library characterization platform designed for standard cells, multi‑bit cells, custom cells, and complex I/Os. It unifies three traditionally separate tasks into a single high‑performance flow:

Characterization
Process variation modeling (LVF)
Library validation

Key Capabilities

Simplified Flow

Run everything in a single session to characterize and model libraries across multiple PVT corners.
Minimum changes required to transition from a legacy single PVT flow to a multi-PVT (MPVT) flow.

Consistency

One consistent setup applied across all PVTs (same methodology, same configuration structure).
Uniform output structure for all generated LIBs across PVT corners, ensuring easier validation and integration.

Performance

Reuse preprocessing artifacts (e.g., vector database) across PVTs to avoid repeated work.
Reuse driver characterization results (e.g., driver waveform database) to accelerate repeated corners.
Better compute efficiency: maximize farm throughput via smart job distribution and parallel execution using Bolt.

Why Liberate Trio Matters

Liberate Trio eliminates traditional characterization bottlenecks by making the flow fast, scalable, and consistent across all PVTs.

Faster turnaround: Parallel multi‑PVT execution significantly reduces runtime
Consistent libraries: Single unified flow for nominal + LVF ensures better correlation
Scalable with Bolt: Efficient job distribution across farm/cloud enables high parallelism
Smarter resource usage: Reuse of data + optimized scheduling improves utilization
Full visibility: Real-time monitoring with quick failure recovery
Efficient recharacterization: Quickly rerun only impacted cells/corners instead of full characterization

Bolt Advantage

Bolt is the engine behind Trio’s scalabilitY. It keeps the farm busy by dynamically distributing jobs to available nodes, load‑balancing across machines, and rerouting failed tasks so large MPVT runs complete faster and more reliably.

Learn How to Do Multi‑PVT Characterization with Liberate Trio

Our MnPVT Characterization of Standard Cells Using Liberate Trio course takes you from fundamentals to hands‑on implementation, covering:

Liberate Trio and Bolt mechanism
Multi-PVT characterization using Liberate Trio
Recovery characterization flow in Liberate Trio
Debugging and validation techniques in Liberate Trio

The course is tightly aligned with the Liberate Trio ecosystem, emphasizing:

Parallel MPVT execution for faster turnaround
Reuse mechanisms (vector/driver databases) for efficiency
Bolt‑based job distribution for scalable compute utilization
Recharacterization flows to update only impacted cells/corners

Ready to Master Standard Cell Characterization?

For lab instructions and a downloadable design, enroll in the online training courses of your interest, MnPVT Characterization of Standard Cells Using Liberate Trio.

Related Resources

Training Bytes (Video Channel)

Online Course

MnPVT Characterization of Standard Cells Using Liberate Trio

Characterizing Standard Cells Using Liberate

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Note: Some of the above links are accessible only to Cadence customers who have a valid login ID for the Cadence Learning and Support Portal.

Do You Have Access to the Cadence Support Portal?

If not, follow the steps below to create your account.

On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
You will need an email address and host ID in order to sign up.
If you need help with registration, contact support@cadence.com.

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If you have questions about courses, schedules, online, public, or live onsite training, reach out to us at Cadence Training.

Take the Accelerated Way

Thanks for reading, wishing you faster, smarter characterization ahead.

Rajashekharayya Hiremath

Lead Education Application Engineer

Virtuoso Studio: Excellent XL – Automated Layout XL Binding from LVS Data

2026-05-15T05:32:00Z

Click here to discover how Virtuoso Studio IC25.1 uses LVS svdb data for automated Layout XL binding, transforming hierarchical designs from LVS-clean to XL-compliant.(read more)

Analog Circuit Modeling Using Verilog-A within Virtuoso: A Video Series

2026-05-07T05:46:00Z

A Practical Video Series that connects Verilog‑A Modeling to Real Circuit Behavior, covering Devices, Data Converters, Signal Generators, and Digital Models.(read more)

Legacy Node to Advanced Silicon: Schematic Migration in Cadence Virtuoso Studio

2026-05-04T08:00:00Z

In today’s fast-paced semiconductor industry, technology nodes evolve quickly—yet analog designs often have long, productive lives. A carefully tuned amplifier, data converter, or IP block can often be reused across multiple process nodes and even across different foundries. This is where schematic migration becomes essential. Schematic migration is now a crucial strategy for modern analog design reuse.

Schematic migration involves transferring a schematic from a source technology (source PDK) to a target technology (target PDK) while maintaining:

Circuit topology and hierarchy
Device intent and parameter relationships
Connectivity and bulk handling
Readiness for simulation

In Virtuoso Studio, schematic migration is part of the Custom Design Migration flow, which also includes layout migration. The schematic phase sets the foundation by creating a clean, well-mapped, connectivity-accurate target schematic that can later guide layout migration and verification.

Design teams depend on schematic migration for several practical reasons:

Advancing technological nodes
Porting across foundries
Reusing IP and scaling products
Reducing risk and saving time

Virtuoso Schematic Migration directly addresses these issues by automating repetitive tasks while allowing designers to retain control over key decisions.

Schematic migration is now a crucial strategy for modern analog design reuse.

With Cadence Virtuoso Schematic Migration, designers can:

Confidently transfer designs across different technologies
Minimize manual effort and migration risks
Preserve connectivity, parameters, and simulation intent
Expand migration from individual cells to entire libraries

Whether upgrading nodes, changing foundries, or reusing proven IP, schematic migration enables faster progress without compromising quality, promising quality.

Want to Learn More?

For lab instructions and a downloadable design, enroll in the online training courses of your interest:

Analog Custom Design Migration Using Virtuoso Studio

Training is also available as a blended or live class.

Note: Access to some training links is limited, they are accessible only to the Cadence customers who have a valid login ID for the Cadence Learning and Support Portal.

Do You Have Access to the Cadence Support Portal?

If not, follow the steps below to create your account.

On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
You will need an email address and host ID in order to sign up.
If you need help with registration, contact support@cadence.com.

To stay up-to-date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails.

If you have questions about courses, schedules, online, public, or live onsite training, reach out to us at Cadence Training.

Become Cadence Certified

Cadence Training Services is now offering digital badges for its training courses. These badges indicate your proficiency in a specific technology or skill, allowing you to validate your expertise to potential employers or managers. You can easily add these digital badges to your email signature or social media profiles like Facebook or LinkedIn to highlight your skills and expertise. To become Cadence Certified, you can find additional information here. Go straight to the course exam at the Learning and Support Portal.

Online Course

Rapid Action Kits

Take the Accelerated Way

Accelerated Learning courses are marked with this symbol in our Learning Maps.

About Knowledge Booster Training Bytes

"Knowledge Booster Training Bytes" is an online journal that provides information about Cadence Training videos, online courses, and upcoming webinars that are available on the Cadence Learning and Support portal. This blog category offers direct links to these videos, courses, and other related materials on a regular basis.

Sai Darshan S Nishani

Sr. Education Application Engineer

New Spectre AMS Designer Features in XCELIUM 26.03

2026-04-27T20:50:00Z

The Spectre AMS Designer features are now available through the XCELIUM 26.03 release for download at Cadence Downloads. For information on supported platforms and other release compatibility information, see the README.txt file in the installation hierarchy.(read more)

Accurate S-Parameter Simulations Using Spectre Simulator in Virtuoso Studio

2026-04-27T19:10:00Z

Introduction: Designing Beyond DC and Time Domain Limits

Imagine validating high-speed interconnect or RF block operating in the multi-GHz range. Traditional modeling and simulation approaches quickly reach their limits when used to validate high speed interconnect or RF blocks operating in the multi-GHz range. When signals begin to propagate like waves, ringing and reflection dominate behavior and frequency-dependent losses become significant, resulting in issues that are only identified after integration..

In these designs, engineers use S-Parameters to describe how signals behave as traveling waves across ports, rather than simple voltages and currents at nodes. This representation is essential for modeling RF blocks, transmission lines, packages, and structures extracted using electromagnetic (EM) simulations.

The training course "S-Parameter Simulations Using Spectre in Virtuoso Studio" aims to help designers accurately model, validate, analyze, and debug S-Parameters within the Virtuoso and Spectre simulation environments. It bridges theoretical understanding with simulation-ready workflows.

Why S-Parameter Simulation Is Essential

S-Parameters are often generated from EM solvers or measured data and then reused across multiple designs. However, poor quality S-Parameter data can lead to serious downstream issues, as described in the table below.

Common Challenges Without Proper S-Parameter Validation

Challenge	Impact on Simulation
Non‑causal data	Nonphysical time domain behavior
Passivity violations	Instability in transient simulations
Insufficient bandwidth	Inaccurate gain and reflection metrics
Poor model fitting	Spectre convergence failures

Suggested S‑Parameter Simulation Flow in Virtuoso and Spectre

This workflow ensures that Spectre-compatible, high-quality S-parameters are utilized in simulations.

The training course "S-Parameter Simulations Using Spectre in Virtuoso Studio" provides designers with the knowledge and tools necessary to work effectively with frequency-domain models in modern high-speed and RF designs. Instead of viewing S-Parameters as opaque data files, this course teaches engineers how to understand, visualize, validate, and debug them using Cadence-supported workflows.

Topics Covered in the Course

1. Introduction to S-Parameters: The course begins with foundational concepts, including:

What S-Parameters represent in frequency domain analysis
Reflection and transmission behavior across ports
Understanding magnitude and phase as part of RF characterization

All the learners—whether from RF or mixed-signal backgrounds—share a common baseline.

2. S-Parameter Modeling and Small-Signal Analysis in Spectre: The core of the course is using S-Parameters directly within the Spectre simulator. Topics include:

S-Parameter modeling best practices
Performing small-signal S-Parameter analysis
Understanding how Spectre consumes and interprets S-Parameter data

This section connects abstract S-Parameter modeling to real simulation workflows.

3. S-Parameter Quality Checking and Fitting Tool: One of the most important components of the course is the S-Parameter Quality Checking and Fitting Tool, designed to:

Provide EM modelers with suggestions for more effective extraction
Detect causality, passivity, and bandwidth issues
Identify problematic S-Parameter datasets early
Generate reliable Rational Fit Models (RFMs) for simulation use

The tool helps reduce downstream simulation failures by ensuring only high-quality S-Parameter data reaches Spectre.

4. Debugging and Comparing S-Parameters: In this course, you will:

Debug issues found during S-Parameter checking
Compare multiple S-Parameter datasets
Evaluate differences between EM extracted, fitted, and measured data

These capabilities are critical when validating models across different extraction or measurement sources.

5. Working with MDIF Data: The final section of the course covers running the S-Parameter Quality Checking and Fitting tool on the Measurement Data Interface File (MDIF) formats.

For more details, kindly navigate to the training: S-Parameter Simulations Using Spectre in Virtuoso Studio

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How to Enroll

This link gives you more information regarding this course, and the link to enroll: S-Parameter Simulations Using Spectre in Virtuoso Studio.

This course includes slides, audio instruction, and downloadable lab exercises, in line with the lecture content.

Earn Your Badge

This training has a Digital Badge. You can earn this badge by passing the exam for this course. Training is also available as "Blended" or "Live".

Note: Some of the above links are accessible only to Cadence customers who have a valid login ID for the Cadence ASK Portal.

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On the Cadence ASK portal, select Register Now and provide the requested information on the Registration page.
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If you need help with registration, contact ask@cadence.com.

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Related Resources

Blogs	Come Join Us and Learn from the Cadence Training Offerings Your Skills Deserve a Passport: Showcase Your Expertise with Digital Badges The Year That Was: Knowledge Booster Training Bytes Blog and Video Highlights from 2024 Knowledge Booster Training Bytes – Find and Enroll in a Cadence Online Training Course
Online Courses	Virtuoso Schematic Editor S1: Creating Design Schematics Virtuoso Schematic Editor S2: Navigating and Capturing Design Intent Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis Spectre Simulator Fundamentals S1: Spectre Basics Spectre Simulator Fundamentals S2: Large-Signal Analyses Spectre Simulator Fundamentals S3: Small-Signal Analyses High-Performance Spectre Simulation Large-Signal RF Analyses Using Harmonic Balance and Shooting Newton Small-Signal RF Analyses Using Harmonic Balance and Shooting Newton
Training Bytes	S-Parameter Assistant in Virtuoso: Plotting Device Parameters from S-Parameter Data S‑Parameter Assistant in Virtuoso: Supported Files, Devices, and Calculations S-Parameter Assistant in Virtuoso: Illustrating Supported Device Types and Practical Example
Product Manuals	Spectre Circuit Simulator and Accelerated Parallel Simulator RF Analysis in ADE Explorer User Guide Product Version 25.1 Spectre Circuit Simulator and Accelerated Parallel Simulator RF Analysis in ADE Explorer Workshop Product Version 25.1

Virtuoso Studio: Layout Editor Productivity Enhancements Blog Series: Part 1

2026-04-24T18:30:00Z

Discover how new Group Array enhancements in Virtuoso Studio IC25.1 streamline editing, boost layout productivity, and simplify managing repeated structures.(read more)

Virtuoso Studio IC25.1 ISR5 Now Available

2026-04-22T20:00:00Z

Virtuoso Studio IC25.1 ISR5 production release is now available for download.(read more)

Virtuoso Studio: Excellent XL- Layout XL Tools for Faster LVS Closure

2026-04-16T20:45:00Z

Ensure your layout perfectly matches the schematic. Click here to discover how the latest Layout XL tools simplify LVS verification and help you achieve faster closure.(read more)

Quantus Assistant: Your AI Copilot for RC Extraction

2026-04-11T21:30:00Z

An AI-powered copilot for Quantus that answers RC extraction questions in plain language, speeds learning, and helps sign-off extraction faster with confidence.(read more)

Animate in Virtuoso Studio: Accelerating Analog Layout Prototyping with It!

2026-03-26T04:27:00Z

The blog introduces Animate in Virtuoso Studio as a powerful analog virtual prototyping capability that brings parametric awareness and early layout visualization directly into the schematic stage, reducing the need for lengthy manual iterations. By generating and comparing multiple layout variants with key metrics early in the flow, Animate helps designers identify issues sooner, minimize rework, and converge on high‑quality layouts faster. The post also highlights a series of short demo videos designed to help users quickly get productive with Animate workflows.(read more)