<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Managing Peak EDA Demands with Micron&amp;#39;s Hybrid-Cloud Model</title><link>/cadence_blogs_8/b/cloud/posts/managing-peak-eda-demands-with-hybrid-cloud-model</link><description>In system-on-chip (SoC) design, everything is scaling except the time to market. This includes the number of transistors, number of simulations, and functionality. Completing more simulations in a short time is mandatory to keep up with the reduced t</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator></channel></rss>