Corporate News

Accelerating AI Silicon Design with AI-Driven Flows

2026-09-09T08:10:00Z

AI silicon complexity is rising faster than engineering teams can scale with traditional workflows. As designs push into advanced nodes, chiplets, and 3D-IC architectures, how these designs are developed, optimized, and converged become crucial. It i...(read more)

Accelerate Chip Design with Arm Architecture: Cadence EDA Tools on AWS Graviton

2026-09-08T13:00:00Z

Cadence has qualified its full EDA flow on Arm-based AWS Graviton CPUs, and Annapurna Labs is already using the digital implementation and signoff portion in production. The semiconductor industry is entering a new phase, defined by AI-scale comple...(read more)

Advanced AI Scaling with 3D-IC and Heterogeneous Integration

2026-09-01T20:15:00Z

As AI and high‑performance computing (HPC) designs advance at leading-edge nodes, design innovation is increasingly extending beyond individual dies to multi‑die and heterogeneous integration enabled by 3D‑IC technologies. However, moving beyond trad...(read more)

OLogic: Engineering Smarter Robots and Edge AI Devices with Cadence

2026-08-27T16:00:00Z

As AI moves beyond the cloud and into robots, smart appliances, and connected devices, engineering teams face growing challenges in designing compact, high-performance hardware. OLogic, a product development company with deep expertise in electronics...(read more)

Helping Physical AI See the Unseen: How EYE4NIR Is Advancing SWIR Imaging

2026-08-20T16:00:00Z

Imagine driving through dense fog yet being able to see clearly beyond what the human eye can detect. That's the vision behind EYE4NIR, a company developing innovative imaging technology that combines visible and short-wave infrared (SWIR) sensin...(read more)

Honda + Cadence = Physical AI (part 3): Creating a Chip the World Has Never Seen

2026-08-19T15:00:00Z

Hello everyone. I'm Kentaro Komori, an engineer in the Semiconductor Research at HGR. In this article, I'd like to introduce Cadence that is our design partner and make the development of next-gen AI chip chips for physical AI. In the age of...(read more)

See AuraStack AI Super Agent in Action!

2026-08-18T14:30:00Z

Modern AI systems are pushing electronic design into a new phase of complexity. High-bandwidth memory, advanced packaging, dense power delivery networks, and high-speed interconnects require engineers to optimize electrical, thermal, mechanical, and ...(read more)

DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality

2026-08-07T15:00:00Z

Every year, Design Automation Conference (DAC) brings big announcements, packed demos, and deep technical conversations—and this year at DAC 2026, the inflection point was AI moving from point-task assistance to workflow-level autonomy. Across ...(read more)

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

2026-07-31T23:00:00Z

Today, AI infrastructure is driving a fundamental shift in semiconductor design. Delivering the next generation of AI systems requires more than advanced process technology; it demands seamless integration across chiplets, 3D-ICs, advanced packaging...(read more)

AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP

2026-07-30T20:20:00Z

As AI workloads scale in size, complexity, and performance requirements, delivering advanced‑node silicon becomes increasingly demanding, as there is little room for uncertainty. Semiconductor teams must move faster while minimizing risk, as advanced...(read more)

HPE: Designing Data Centers for AI at Scale

2026-07-30T15:30:00Z

One of the biggest inefficiencies in modern data centers is the disconnect between IT systems and the physical facility. Servers, storage, and networking are often managed separately from cooling, power, and space planning. As a result, many data cen...(read more)

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

2026-07-27T13:05:00Z

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital and custom design enablement, advanced packaging support, and power delivery-optimized flows for AI, HPC, mobile, and future aerospace applications. Cadence's AI-driven ...(read more)

The Autonomous Chip-to-System Engineer Has Arrived

2026-07-27T01:00:00Z

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon-to-system agentic AI engineering platform For decades, the semiconductor industry has tackled growing complexity the same way: add more engineers, throw more compute ...(read more)

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

2026-07-22T21:00:00Z

AI infrastructure demands are changing what semiconductor design must solve. The challenge is no longer only about creating faster silicon; it is about designing complete systems where silicon, advanced packaging, PCB, power delivery, thermal behavi...(read more)

Jilin University Accelerates Student Racing Success Using Fidelity CFD Software

2026-07-21T13:30:00Z

Founded in 1955, the College of Automotive Engineering at Jilin University has a long tradition of developing automotive talent. That commitment extends beyond the classroom through its student racing program, established in 2007, which has become on...(read more)